Abstract: An equalizer for equalizing an input signal includes an infinitive impulse response (IIR) filtering portion for filtering the input signal to produce N filtered outputs; a gain-adjusting portion coupled to the IIR filtering portion with N gains for adjusting the N filtered outputs to produce N gained outputs, respectively; and an adder for summing the N gained outputs to generate an equalized output signal. N is an integer larger than 2.

Abstract: An audio volume control circuit includes a signal intensity calculating circuit for generating a first signal intensity value corresponding to a signal intensity corresponding to an audio channel data; a low-pass filter for filtering the first signal intensity to generate a second signal intensity value; an averaging unit for averaging the second signal intensity value and previous M?1 second signal intensity values to obtain a third signal intensity value, with M being a natural number greater than 1; a gain calculating circuit for obtaining an original gain value according to the third signal intensity value with reference to the adjustment condition; a buffer for temporarily storing the audio channel data; and an audio volume adjusting circuit for generating an adjustment gain value according to the original gain value to adjust the audio channel data stored in the buffer.

Abstract: A de-interlacing method and controller is provided. The de-interlacing method includes steps of de-interlacing based on an ith odd input pixel row of an odd field and an ith even input pixel row of an even field to generate an ith odd output pixel row, where i is a natural number; de-interlacing based on the ith even input pixel row and an (i+1)th odd input pixel row of the odd field to generate an ith even output pixel row; and adjusting i and repeating the above steps to generate a complete interpolated frame.

Abstract: An audio volume control circuit includes a signal intensity calculating circuit for generating a first signal intensity value corresponding to a signal intensity corresponding to an audio channel data; a low-pass filter for filtering the first signal intensity to generate a second signal intensity value; an averaging unit for averaging the second signal intensity value and previous M?1 second signal intensity values to obtain a third signal intensity value, with M being a natural number greater than 1; a gain calculating circuit for obtaining an original gain value according to the third signal intensity value with reference to the adjustment condition; a buffer for temporarily storing the audio channel data; and an audio volume adjusting circuit for generating an adjustment gain value according to the original gain value to adjust the audio channel data stored in the buffer.

Abstract: An audio buffering system in a multimedia receiver includes an audio interface coupled to an incoming audio signal for generating a digital audio signal having transmitted therein a plurality of data words; a first-in-first-out (FIFO) buffer being coupled to the digital audio signal and comprising a plurality of cells being organized sequentially for holding data words of the digital audio signal, wherein a first cell of the FIFO buffer has an input being coupled to the digital audio signal; and a first shift register having a plurality of bits being organized serially, wherein a first bit of the first shift register receives an output from a last bit of the first shift register, and each bit of the first shift register is coupled to a corresponding bit in an outputted data word of the FIFO buffer. The first shift register is loaded with data words outputted from the FIFO buffer.

Abstract: A de-interlacing method and controller is provided. The de-interlacing method includes steps of de-interlacing based on an ith odd input pixel row of an odd field and an ith even input pixel row of an even field to generate an ith odd output pixel row, where i is a natural number; de-interlacing based on the ith even input pixel row and an (i+1)th odd input pixel row of the odd field to generate an ith even output pixel row; and adjusting i and repeating the above steps to generate a complete interpolated frame.

Abstract: An audio processing circuit includes a clock synthesizer, a clock divider, a digital interpolator module, a sampling rate converter and a digital-to-analog converter. The clock synthesizer generates a base clock signal according to a sampling clock signal and a first reference clock signal. The clock divider generates a multiple frequency clock signal according to the base clock signal. The digital interpolator module interpolates a digital audio data according to the multiple frequency clock signal. The sampling rate converter processes the interpolated digital audio data into a re-sampled digital audio data according to the multiple frequency clock signal and a second reference clock signal. The digital-to-analog converter is coupled to the sampling rate converter for converting the re-sampled digital audio data into an analog audio signal according to the second reference clock signal.

Abstract: A de-interlacing device capable of de-interlacing a video field adaptively and associated method, the device includes a video field detector for detecting a video field and for outputting a motion detection parameter, a motion detector for detecting a motion difference between the video frame and at least one video frame neighboring the video frame, and for determining a motion ratio for the motion difference according to the motion detection parameter, and a de-interlacing unit for de-interlacing the video field according to the motion ratio output from the motion detector.

Abstract: An equalizer for equalizing an input signal includes an infinitive impulse response (IIR) filtering portion for filtering the input signal to produce N filtered outputs; a gain-adjusting portion coupled to the IIR filtering portion with N gains for adjusting the N filtered outputs to produce N gained outputs, respectively; and an adder for summing the N gained outputs to generate an equalized output signal. N is an integer larger than 2.

Abstract: An audio processing circuit includes a clock synthesizer, a clock divider, a digital interpolator module, a sampling rate converter and a digital-to-analog converter. The clock synthesizer generates a base clock signal according to a sampling clock signal and a first reference clock signal. The clock divider generates a multiple frequency clock signal according to the base clock signal. The digital interpolator module interpolates a digital audio data according to the multiple frequency clock signal. The sampling rate converter processes the interpolated digital audio data into a re-sampled digital audio data according to the multiple frequency clock signal and a second reference clock signal. The digital-to-analog converter is coupled to the sampling rate converter for converting the re-sampled digital audio data into an analog audio signal according to the second reference clock signal.

Abstract: An audio buffering system in a multimedia receiver includes an audio interface coupled to an incoming audio signal for generating a digital audio signal having transmitted therein a plurality of data words; a first-in-first-out (FIFO) buffer being coupled to the digital audio signal and comprising a plurality of cells being organized sequentially for holding data words of the digital audio signal, wherein a first cell of the FIFO buffer has an input being coupled to the digital audio signal; and a first shift register having a plurality of bits being organized serially, wherein a first bit of the first shift register receives an output from a last bit of the first shift register, and each bit of the first shift register is coupled to a corresponding bit in an outputted data word of the FIFO buffer. The first shift register is loaded with data words outputted from the FIFO buffer.

Abstract: A de-interlacing device capable of de-interlacing a video field adaptively and associated method, the device includes a video field detector for detecting a video field and for outputting a motion detection parameter, a motion detector for detecting a motion difference between the video frame and at least one video frame neighboring the video frame, and for determining a motion ratio for the motion difference according to the motion detection parameter, and a de-interlacing unit for de-interlacing the video field according to the motion ratio output from the motion detector.

Abstract: A method for the processing of video fields is disclosed. The method includes judging similarities of each couple among a plurality of couples of adjacent fields (wherein each couple of fields includes an odd field and an even field; and generated image signals of another format according to a pattern of the similarities and the original video fields. A method of detecting similarities between odd fields and even fields is further disclosed, such that similarities of adjacent interlaced fields can be utilized to judge the format of image source in order to generate progressive high quality frames more efficiently.