Abstract: The present application discloses a cell structure of a super flash comprising: a word line gate, a floating gate, a control gate, and an erase gate. The floating gate comprises a first TiN layer located on a side face of the control gate and a second polysilicon layer formed at the top of the first TiN layer. The second polysilicon layer is in electric contact with the first TiN layer. The erase gate is located at the top of the second polysilicon layer, and the erase gate and the floating gate are spaced from each other by a second inter-gate dielectric layer therebetween. During erasing, the top angle of the second polysilicon layer generates point discharge, thereby reducing an erasing voltage. The present application also discloses a method for manufacturing a super flash.

Abstract: The present disclosure relates to air assemblies having an inflation, a deflation, and a closed state for use with inflatable products, such as air mattresses. Specifically, the present disclosure relates to air assemblies where the configuration of the air assembly can be changed manually by a user by operating a directional control valve to inflate, deflate, or close the inflatable product. The directional control valve may also activate a pump in the inflation and deflation states and deactivate the pump in the closed state.

Abstract: Disclosed are a low-cost high-efficiency drip irrigation system for a cotton field and a use method thereof. The drip irrigation system for a cotton field includes a filtering device and a water supply device; wherein the filtering device adopts different types of single filtering devices or combined filtering devices according to different water source types; the water supply device includes multiple stages of main pipes, submain pipes and laterals; the laterals (a drip irrigation tape with labyrinth on one side or a drip irrigation tape inlaid with emitters inside) are laid on the surface of the ground and located below a mulch film. The drip irrigation system adopts the design of large flow (1.5-3.4 L/h), slightly larger pipe diameter (>75 mm), low water pressure (operating pressure of drip irrigation tape being 0.03-0.07 MPa) and suitable drip irrigation uniformity (80%-90%).

Abstract: The present application discloses a low voltage triggering silicon controlled rectifier which includes: an N well and a P well forming a PN junction, a first P+ region formed in the N well and connected to an anode, and a first N+ region formed in the P well and connected to a cathode. A second P+ region is formed in the N well at the PN junction and diffuses into the P well. A second N+ region is formed in the P well at the PN junction and diffuses into the N well. A first gate structure connected to the anode is formed at the surface of the N well between the first and second P+ regions; and a second gate structure connected to the cathode is formed at the surface of the P well between the first and second N+ regions.

Abstract: An array substrate (100) and a display device. The array substrate (100) includes a bonding area (102). The array substrate (100) includes a substrate (10), a first conductive layer (20) on the substrate (10), a first insulating layer (30) on one side of the first conductive layer (20) away from the substrate (10), and a second conductive layer (40) on one side of the first insulating layer (30) away from the substrate (10). The bonding area (102) is provided with bonding pins (201), and the bonding pin (201) includes a first conductive portion (21) and a second conductive portion (41) located on the side of the first conductive portion (21) away from the substrate (10), the first conductive portion (21) is located in the first conductive layer (20), the second conductive portion (41) is located in the second conductive layer (40), and the first conductive portion (21) is in direct contact with the second conductive portion (41).

Abstract: This invention discloses a medicinal composition includes a non-coding RNA molecule and an antibody targeting a tumor antigen for preventing and/or treating cancer. This invention uses the synergistic combination of a non-coding RNA molecule or its functional variant or homologue, and an antibody targeting a tumor antigen to prevent and/or treat cancer, thereby providing a novel and effective method in preventing and/or treating various cancers.

Abstract: The present disclosure relates to air assemblies having an inflation, a deflation, and a closed state for use with inflatable products, such as air mattresses. Specifically, the present disclosure relates to air assemblies where the configuration of the air assembly can be changed manually by a user by operating a directional control valve to inflate, deflate, or close the inflatable product. The directional control valve may also activate a pump in the inflation and deflation states and deactivate the pump in the closed state.

Abstract: The invention relates to a seating frame for a vehicle seat, the frame comprising a back frame component for supporting a back rest, wherein the back frame component includes a plurality of interconnected reinforcing ribs that form a single unit, and wherein the seating frame is a one-piece injection-molded part made of plastic material. The invention also relates to a process of making such a seating frame. Furthermore, the invention relates to a vehicle seat comprising such a seating frame, and a vehicle comprising such a vehicle seat or such a seating frame.

Abstract: The disclosure discloses a global shutter CMOS image sensor, which adopts non-uniform storage diffusion region doping to reduce the junction leakage at storage points, so as to ensure that with the increase of the depth of photodiodes and the increase of pixels, all carriers in rows read subsequently can be transferred to storage diffusion regions, the loss of the carriers in the storage diffusion regions is not caused when a global shutter transistor is turned on, and the carriers can be completely transferred from the storage diffusion regions to floating diffusion regions through second transfer transistors even if the number of rows of pixel units increases during reading-out row by row. The disclosure further discloses a method for making the global shutter CMOS image sensor.

Abstract: A method for analyzing a correlation between rail transit and direct current (DC) magnetic bias of a transformer includes the steps of, A: obtaining a current of a feed cable and a DC magnetic bias current: measuring the feed cable current in rail transit and the DC magnetic bias current of a transformer in a power grid within a certain period by a monitoring apparatus; B: calculating a characteristic quantity of the feed current within the measurement period based on the obtained current of the feed cable; C: calculating a characteristic quantity of the DC magnetic bias current within the measurement period based on the DC magnetic bias current; and D: calculating a support degree and a confidence coefficient based on the calculated characteristic quantity of the feed current and the calculated characteristic quantity of the DC magnetic bias current, and generating a correlation rule.

Abstract: The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

Abstract: The disclosure discloses a global shutter CMOS image sensor, which adopts non-uniform storage diffusion region doping to reduce the junction leakage at storage points, so as to ensure that with the increase of the depth of photodiodes and the increase of pixels, all carriers in rows read subsequently can be transferred to storage diffusion regions, the loss of the carriers in the storage diffusion regions is not caused when a global shutter transistor is turned on, and the carriers can be completely transferred from the storage diffusion regions to floating diffusion regions through second transfer transistors even if the number of rows of pixel units increases during reading-out row by row. The disclosure further discloses a method for making the global shutter CMOS image sensor.

Abstract: The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.

Abstract: The present invention provides a semiconductor structure for forming a CMOS image sensor. The semiconductor structure includes at least a photodiode formed in the substrate for collecting photoelectrons, and the photodiode has a pinning layer, a first doped region and a second doped region in order from top to bottom in a height direction of the substrate. The semiconductor structure further includes a third doped region located in the substrate corresponding to a laterally extending region of the second doped region. The first doped region has an ion doping concentration greater than the ion doping concentration of the second doped region, the ion doping concentration of the second doped region is greater than the ion doping concentration of the third doped region, and the third doped region is in contact with the second doped region after diffusion. The present invention also provides a method of manufacturing the above-described semiconductor structure.

Abstract: The present invention provides a semiconductor structure for forming a CMOS image sensor. The semiconductor structure includes at least a photodiode formed in the substrate for collecting photoelectrons, and the photodiode has a pinning layer, a first doped region and a second doped region in order from top to bottom in a height direction of the substrate. The semiconductor structure further includes a third doped region located in the substrate corresponding to a laterally extending region of the second doped region. The first doped region has an ion doping concentration greater than the ion doping concentration of the second doped region, the ion doping concentration of the second doped region is greater than the ion doping concentration of the third doped region, and the third doped region is in contact with the second doped region after diffusion. The present invention also provides a method of manufacturing the above-described semiconductor structure.

Abstract: The present application discloses a method for manufacturing a semiconductor device, which includes the following steps: step 1: forming first gate structures on a semiconductor substrate; step 2: performing a first etching process to etch the semiconductor substrate on at least one side of each first gate structure to a certain depth and form a first groove; step 3: performing a stress memorization process, including step 31: forming a stress dielectric layer, the stress dielectric layer covering a peripheral surface of each first gate structure and being filled in the first groove; step 32: performing annealing to transfer the stress of the stress dielectric layer to a channel region; step 33: removing the stress dielectric layer. The present application can increase the effect of transferring the stress of the stress dielectric layer to the channel region, thereby increasing the mobility of channel carriers.

Abstract: The present application discloses a ReRAM device, the bottom surface of a first resistance switching layer is connected with a bottom electrode, and a first groove is formed in the center of the top surface of the first resistance switching layer. A second resistance switching layer is formed on the first resistance switching layer, the center of the bottom surface of the second resistance switching layer is filled downwards into the first groove, and the top surface of the second resistance switching layer is connected with a top electrode. The material of the second resistance switching layer is more conductive than the material of the first resistance switching layer. The present application can maintain the stability of the central conductive filament in the low resistance state. The present application further discloses a method for manufacturing the ReRAM device.

Abstract: The disclosure discloses a global shutter CMOS image sensor, which adopts non-uniform storage diffusion region doping to reduce the junction leakage at storage points, so as to ensure that with the increase of the depth of photodiodes and the increase of pixels, all carriers in rows read subsequently can be transferred to storage diffusion regions, the loss of the carriers in the storage diffusion regions is not caused when a global shutter transistor is turned on, and the carriers can be completely transferred from the storage diffusion regions to floating diffusion regions through second transfer transistors even if the number of rows of pixel units increases during reading-out row by row. The disclosure further discloses a method for making the global shutter CMOS image sensor.

Abstract: The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

Abstract: A method for analyzing a correlation between rail transit and direct current (DC) magnetic bias of a transformer includes the following steps: A: obtaining a current of a feed cable and a DC magnetic bias current: measuring the feed cable current in rail transit and the DC magnetic bias current of a transformer in a power grid within a certain period by a monitoring apparatus; B: calculating a characteristic quantity of the feed current within the measurement period based on the obtained current of the feed cable; C: calculating a characteristic quantity of the DC magnetic bias current within the measurement period based on the DC magnetic bias current; and D: calculating a support degree and a confidence coefficient based on the calculated characteristic quantity of the feed current and the calculated characteristic quantity of the DC magnetic bias current, and generating a correlation rule.