Abstract: An error correcting system is provided. The error correcting system includes an error correcting code (ECC) circuit and a control circuit. The ECC circuit is configured to encode input data received from M input terminals to generate encoded data in response to a write operation, and output the encoded data. The input data includes write data associated with the write operation, and the encoded data includes the input data and associated parity data. The control circuit is coupled to at least one of the M input terminals. When the write operation is directed to a memory device having a data bit width less than M bits, the write data is inputted to a portion of the M input terminals, the control circuit is configured to provide reference data to another portion of the M input terminals, and the write data and the reference data serve as the input data.

Abstract: An error correcting system is provided. The error correcting system includes an error correcting code (ECC) circuit and a control circuit. The ECC circuit is configured to encode input data received from M input terminals to generate encoded data in response to a write operation, and output the encoded data. The input data includes write data associated with the write operation, and the encoded data includes the input data and associated parity data. The control circuit is coupled to at least one of the M input terminals. When the write operation is directed to a memory device having a data bit width less than M bits, the write data is inputted to a portion of the M input terminals, the control circuit is configured to provide reference data to another portion of the M input terminals, and the write data and the reference data serve as the input data.

Abstract: A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.

Abstract: A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.