Abstract: Presented herein are embodiments of an improved asymmetric quantization, which may generally be referred to as improved asymmetric quantization (IAQ) embodiments. IAQ embodiments combine the benefits of conventional asymmetric quantization and symmetric quantization but also provide additional computation efficiencies. Embodiments of IAQ adopt an asymmetric range of the weights of a neural network layer, so they circumvent the limitation of symmetric range of symmetric quantization. Moreover, the inference process of a neural network quantized by an IAQ embodiment is much faster than that of the neural network quantized by conventional asymmetric quantization by quantizing an offset value of each layer.

Abstract: Embodiments of the present disclosure provide a data accessing method and apparatus, and a computer-readable storage medium, and relate to a computer field. The data accessing method includes: obtaining an identification of a virtual function corresponding to a virtual machine of a computing device and an address related to data in a memory to be accessed by the virtual machine, in which the identification of the virtual function and the address are determined based on an access request received from the virtual machine of the computing device; determining a range of storage resource in the memory corresponding to the virtual machine based on the identification; determining whether the address is within the range; and in response to determining that the address is within the range, accessing the data related to the address.

Abstract: Embodiments of the present disclosure relate to a method, an apparatus, an electronic device and a computer readable storage medium for determining connection relationships among a plurality of chips. The method includes determining identity information of a plurality of chips managed by a host, the plurality of chips being connected by respective inter-chip communication interfaces for inter-chip communication. The method further includes allowing one or more of the plurality of chips to acquire identity information of other chips connected to the inter-chip communication interface of the one or more chips. The method further includes reading identity information of the other chips by means of a management interface of the one or more chips with regard to communicating with the host, so as to determine connection relationships among the plurality of chips.

Abstract: An automatic processing system, a system on chip and a method for monitoring a processing module are described herein. The automatic driving processing system comprises: an automatic driving processing module, configured for receiving an input data stream and processing the input data stream based on a deep learning model so as to generate a processing result; a fault detection module, configured for generating a control signal and a fault detection stimulating data stream, and receiving the processing result from the automatic driving processing module; and a multi-way selection module, configured for receiving an automatic driving data stream as well as the control signal and the fault detection stimulating data stream, and selectively outputting the automatic driving data stream or the fault detection stimulating data stream to the automatic driving processing module based on the control signal, as an input data stream.

Abstract: A method is provided for forming a poly-crystalline silicon film on a substrate. In one embodiment, the method comprises positioning a substrate within a processing chamber, heating the processing chamber to a deposition temperature, introducing a first silicon precursor into the processing chamber to form a buffer layer including crystal nuclei, introducing a second silicon precursor into the processing chamber to form a polysilicon film on the buffer layer, and then annealing the polysilicon film and the buffer layer.