Abstract: The present disclosure relates to a diffusion plate support frame, a direct-type backlight module and a display apparatus. The diffusion plate support frame includes: a bottom plate; and one or more support portions, each of the one or more support portions is located on the bottom plate and comprises: a first buffer structure, and a support pin. The first buffer structure is located between the bottom plate and the support pin, and the first buffer structure is used for buffering pressure when subjected to a pressure applied by the support pin towards the bottom plate.

Abstract: The present disclosure relates to a diffusion plate support frame, a direct-type backlight module and a display apparatus. The diffusion plate support frame includes: a bottom plate; and one or more support portions, each of the one or more support portions is located on the bottom plate and comprises: a first buffer structure, and a support pin.

Abstract: The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously.

Abstract: The present invention provides a tapping hammer for tapping test, which can help a user to accurately control the tapping force during a tapping test. The tapping hammer comprises a hammerhead and a handle supporting the hammerhead, and further comprises an alarm, a power source and a conductor, a hollowed-out region is provided in the interior of the hammerhead, the hammerhead is elastically deformable and electrically connected to a first electrode of the power source; the conductor is fixed in the interior hollowed-out region, not electrically connected to the hammerhead while no tapping force is exerted on the hammerhead and electrically connected to the hammerhead while a tapping force larger than a certain amount is exerted on the hammerhead; a first electrode of the alarm is connected to the conductor, a second electrode of the alarm is connected to a second electrode of the power source.

Abstract: The present invention provides a tapping hammer for tapping test, which can help a user to accurately control the tapping force during a tapping test. The tapping hammer comprises a hammerhead and a handle supporting the hammerhead, and further comprises an alarm, a power source and a conductor, a hollowed-out region is provided in the interior of the hammerhead, the hammerhead is elastically deformable and electrically connected to a first electrode of the power source; the conductor is fixed in the interior hollowed-out region, not electrically connected to the hammerhead while no tapping force is exerted on the hammerhead and electrically connected to the hammerhead while a tapping force larger than a certain amount is exerted on the hammerhead; a first electrode of the alarm is connected to the conductor, a second electrode of the alarm is connected to a second electrode of the power source.

Abstract: The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously.