Patents by Inventor Zhicai XU

Zhicai XU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098326
    Abstract: The present disclosure provides a driving method of a display panel, the display panel including a plurality of pixels, each row of pixels correspond to a gate line, each column of pixels correspond to a data line, the driving method including: comparing a current frame of image with a previous frame of image to determine a non-changing row of the pixels, contents displayed by each pixel in the non-changing row for the current frame of image and contents displayed by each pixel in the non-changing row for the previous frame of image are the same; selecting a non-charging row from the non-changing row according to a predetermined time; providing, when displaying the current frame of image, an invalid signal to the gate line of the non-charging row during a scanning time for the gate line of the non-charging row to not to charge the non-charging row.
    Type: Application
    Filed: August 9, 2019
    Publication date: March 26, 2020
    Inventors: Ying ZHANG, Sijun LEI, Xu LU, Xianyong GAO, Shoujun XIAO, Yifan HUANGFU, Zhicai XU, Bo RAN, Yongli GE
  • Patent number: 10585317
    Abstract: The present disclosure relates to a COA substrate and a manufacturing method thereof, a display device. The COA substrate includes the following layers in a wiring region: a first conduction layer including a signal wire lead; an insulation layer having a first via to expose the signal wire lead; a second conduction layer including a first metal pattern with a second via; a flat layer having a hollowed-out region; and a connection pattern. The second via is at least in part located within the hollowed-out region, and orthographic projections of a border of a portion of the second via which is located within the hollowed-out region and a border of the first via on the base substrate overlap. The connection pattern extends through the first via and the second via and connects to the signal wire lead.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 10, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhicai Xu, Kui Zhang, Hui Li, Mengqiu Liu
  • Publication number: 20200058362
    Abstract: A shift register unit, a driving method and a gate driving circuit are provided. The shift register unit includes a pull-up node control circuit, a pull-down node control circuit, a capacitor circuit, an output circuit and a noise reduction adjustment circuit. The noise reduction adjustment circuit is connected to a pull-down node and a first level input end, and configured to reduce an increasing rate of a potential at the pull-down node within a noise reduction time period of a maintenance phase, and reduce a decreasing rate of the potential at the pull-down node within a non-noise-reduction time period of the maintenance phase.
    Type: Application
    Filed: March 12, 2019
    Publication date: February 20, 2020
    Applicants: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhicai XU, Jia SUN, Lijun XIAO
  • Patent number: 10444579
    Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of the display substrate includes: forming an insulation layer on a base substrate, the base substrate including a display area and a peripheral area; and forming a planarization film on the insulation layer; performing a patterning process to the planarization film to form a planarization layer with a first thickness in the display area, a planarization layer with a second thickness in the peripheral area, and a first via hole in the planarization layer with the second thickness, the second thickness being less than the first thickness, and performing an etching process on the peripheral area to thin or remove the planarization layer is with the second thickness, and forming a second via hole corresponding to the first via hole in the insulation layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 15, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaoyuan Wang, Yan Fang, Kui Zhang, Zhicai Xu, Ming Deng
  • Publication number: 20190196288
    Abstract: Embodiments of the present disclosure provide an array substrate, a method of manufacturing the same, a liquid crystal display panel, and a display device. The array substrate includes: a base substrate, a data line disposed on the base substrate and a pixel electrode layer disposed on a layer in which the data line is located. The pixel electrode layer includes a plurality of columns of pixel electrodes that are spaced apart from one another. An orthographic projection of the data line on the base substrate covers an orthographic projection of a gap between two adjacent columns of pixel electrodes on the base substrate, and a width of the data line is greater than a width of the gap between two adjacent columns of pixel electrodes.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 27, 2019
    Inventors: Zhicai Xu, Ruilin Bi, Jiandong Guo, Zhulin Liu, Shouqiang Zhang, Kui Zhang
  • Publication number: 20190094598
    Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of the display substrate includes: forming an insulation layer on a base substrate, the base substrate including a display area and a peripheral area and forming a planarization film on the insulation layer; performing a patterning process to the planarization film to form a planarization layer with a first thickness in the display area, a planarization layer with a second thickness in the peripheral area, and a first via hole in the planarization layer with the second thickness, the second thickness being less than the first thickness, and performing an etching process on the peripheral area to thin or remove the planarization layer is with the second thickness, and forming a second via hole corresponding to the first via hole in the insulation layer.
    Type: Application
    Filed: September 29, 2017
    Publication date: March 28, 2019
    Inventors: Xiaoyuan WANG, Yan FANG, Kui ZHANG, Zhicai XU, Ming DENG
  • Publication number: 20180284507
    Abstract: The present disclosure relates to a COA substrate and a manufacturing method thereof, a display device. The COA substrate includes the following layers in a wiring region: a first conduction layer including a signal wire lead; an insulation layer having a first via to expose the signal wire lead; a second conduction layer including a first metal pattern with a second via; a flat layer having a hollowed-out region; and a connection pattern. The second via is at least in part located within the hollowed-out region, and orthographic projections of a border of a portion of the second via which is located within the hollowed-out region and a border of the first via on the base substrate overlap. The connection pattern extends through the first via and the second via and connects to the signal wire lead.
    Type: Application
    Filed: November 27, 2017
    Publication date: October 4, 2018
    Inventors: Zhicai XU, Kui ZHANG, Hui LI, Mengqiu LIU