Patents by Inventor Zhichen Zhang

Zhichen Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240138606
    Abstract: An opening and closing device for a curtain mounted on a guiding part, the guiding part is provided with the curtain; the opening and closing device is used for driving automatically the opening and closing of the curtain; the opening and closing device includes a mainframe and a connecting mechanism. The mainframe includes a shell, a driver, and a driving wheel; the driving wheel and the driver are mounted in the shell, the driver drives the driving wheel to rotate. The connecting mechanism includes a hanging piece and a bracket; a first end of the bracket is inserted into the shell, the hanging piece is movably connected with a second end of the bracket and hung on the guiding part; the hanging piece can be moved vertically relative to the bracket so that the driving wheel is attached closely to the outer wall of the guiding part.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: Zhichen Li, Wei Hou, Yang Pan, Haobo Zhang, Chao Ma
  • Publication number: 20240145026
    Abstract: The present invention discloses a protein transformation method based on an amino acid knowledge graph and active learning, including: building an amino acid knowledge graph based on biochemical attributes of amino acids; enhancing protein data in combination with the amino acid knowledge graph to obtain enhanced protein data, and performing representation learning to obtain first enhanced protein representations; performing representation learning on the protein data or the protein data and the amino acid knowledge graph by using a pre-trained protein model to obtain second enhanced protein representations; synthesizing the first enhanced protein representations and the second enhanced protein representations to obtain enhanced protein representations; taking the enhanced protein representations as samples, and through active learning, screening out representative samples from the samples, manually annotating protein properties, and training a protein property prediction model by using the manually annotated
    Type: Application
    Filed: October 21, 2022
    Publication date: May 2, 2024
    Inventors: QIANG ZHANG, MING QIN, ZHICHEN GONG, HUAJUN CHEN
  • Patent number: 11149361
    Abstract: Preparation methods of a high modulus carbon fiber (HMCF) and a precursor (mesophase pitch (MP)) thereof are provided. The preparation method of MP includes: separating components with a molecular weight distribution (MWD) of 400 to 1,000 from a heavy oil raw material through size-exclusion chromatography (SEC); subjecting the components to ion-exchange chromatography (IEC) to obtain modified feedstock oil, where, the components are passed through macroporous cation-exchange and anion-exchange resins in sequence to remove acidic and alkaline components; and subjecting the modified feedstock oil to thermal polycondensation and carbonization to obtain high-quality MP with prominent spinnability. With high mesophase content, low softening point, low viscosity, and prominent meltability and spinnability, the obtained MP is a high-quality raw material for preparing HMCFs. The obtained MP can be subjected to melt spinning, pre-oxidation, carbonization, and graphitization to obtain an MP-based HMCF.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 19, 2021
    Assignee: CHINA UNIVERSITY OF PETROLEUM
    Inventors: Dong Liu, Xin Gong, Bin Lou, Jun Li, Zhihao Li, Nan Shi, Fushan Wen, Hui Du, Zhaojun Chen, Changlong Yin, Xiujie Yang, Luning Chai, Zhichen Zhang, Enqiang Yu, Yu'e Fu, Huizhi Yuan, Jianguo Zhang, Zhiqing Ma, Chong Jiao, Yonggang Cao
  • Patent number: 9733302
    Abstract: An integrated circuit (IC) having a heat-generating element, such as a power MOSFET, a current-carrying conductor coupled to the heat-generating element, a sense conductor adjacent the current-carrying conductor, and a failure-detection circuit coupled to the sense conductor. When thermal cycling of the IC causes the resistance of the sense conductor to become greater than a temperature-dependent threshold value, the failure-detection circuit generates a signal indicating that the integrated circuit will soon fail. The resistance of the sense conductor is determined by injecting a current into the sense conductor to generate a voltage. The temperature-dependent threshold value is a voltage generated by injecting a current into a reference conductor disposed away from the current-carrying and sense conductors. A voltage comparator compares the two voltages to generate the output.
    Type: Grant
    Filed: September 6, 2015
    Date of Patent: August 15, 2017
    Assignee: NXP USA, INC.
    Inventors: Zhichen Zhang, John M. Pigott, Chuanzheng Wang, Qilin Zhang, Michael J. Zunino
  • Publication number: 20160216318
    Abstract: An integrated circuit (IC) having a heat-generating element, such as a power MOSFET, a current-carrying conductor coupled to the heat-generating element, a sense conductor adjacent the current-carrying conductor, and a failure-detection circuit coupled to the sense conductor. When thermal cycling of the IC causes the resistance of the sense conductor to become greater than a temperature-dependent threshold value, the failure-detection circuit generates a signal indicating that the integrated circuit will soon fail. The resistance of the sense conductor is determined by injecting a current into the sense conductor to generate a voltage. The temperature-dependent threshold value is a voltage generated by injecting a current into a reference conductor disposed away from the current-carrying and sense conductors. A voltage comparator compares the two voltages to generate the output.
    Type: Application
    Filed: September 6, 2015
    Publication date: July 28, 2016
    Inventors: Zhichen Zhang, John M. Pigott, Chuanzheng Wang, Qilin Zhang, Michael J. Zunino
  • Patent number: 9222968
    Abstract: A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit. When the degradation test transistor is inserted into the amplifier circuit, an output signal is generated that is indicative of stress degradation of the integrated circuit.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: December 29, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhichen Zhang, Chuanzheng Wang, Qilin Zhang
  • Publication number: 20150234961
    Abstract: A method for integrated circuit reliability aging simulation includes dividing a target time period into N stages including a first stage and a second stage; obtaining first parameter values of a reliability model for the first stage; performing a first simulation on the circuit based on the reliability model and the first parameter values to obtain first aging results; obtaining second parameter values of the reliability model for the second stage; and performing a second simulation on the circuit based on the reliability model and the second parameter values to obtain second aging results.
    Type: Application
    Filed: December 2, 2014
    Publication date: August 20, 2015
    Inventors: Zhichen Zhang, Xavier Hours, Mehul D. Shroff, Chuanzheng Wang, Qilin Zhang
  • Publication number: 20140191777
    Abstract: A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit. When the degradation test transistor is inserted into the amplifier circuit, an output signal is generated that is indicative of stress degradation of the integrated circuit.
    Type: Application
    Filed: November 11, 2013
    Publication date: July 10, 2014
    Inventors: Zhichen Zhang, Chuanzheng Wang, Qilin Zhang
  • Patent number: 8479130
    Abstract: A method of designing an integrated circuit (IC) includes simulating aging evolution of the IC by providing a standard cells library, and a device activity file of device electrical activity in the standard cells as a function of electrical activity at the pins of the standard cells, taking into account Hot Carrier Injection, Negative Bias Temperature Instability, and gate oxide breakdown. A standard cell evolution file is provided that stores electrical characteristic aging data of standard cells. An instance activity file is provided of simulated electrical activity at the pins of individual instances of the cells in the IC. The instance activity file and the device activity file are used to analyze device activity and consequent aging evolution of the devices, and then generate data for consequent aging evolution of the IC. The IC design can then be modified to account for the aging evolution.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: July 2, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhichen Zhang, Chuanzheng Wang