Patents by Inventor Zhida Lan
Zhida Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9704920Abstract: A memory device includes at least one memory cell. The at least one memory cell includes a steering element, a resistive memory element, and a tunneling dielectric element located between the steering element and the resistive memory element.Type: GrantFiled: October 27, 2015Date of Patent: July 11, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Abhijit Bandyopadhyay, Venkatagirish Nagavarapu, Xiao Li, Zhida Lan, Michael Konevecki
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Publication number: 20170117324Abstract: A memory device includes at least one memory cell. The at least one memory cell includes a steering element, a resistive memory element, and a tunneling dielectric element located between the steering element and the resistive memory element.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: Abhijit BANDYOPADHYAY, Venkatagirish NAGAVARAPU, Xiao LI, Zhida LAN, Michael KONEVECKI
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Patent number: 9576660Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.Type: GrantFiled: January 14, 2016Date of Patent: February 21, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhida Lan, Roy E. Scheuerlein, Tong Zhang, Kun Hou, Perumal Ratnam
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Patent number: 9472758Abstract: The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.Type: GrantFiled: November 11, 2014Date of Patent: October 18, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhida Lan, Abhijit Bandyopadhyay, Christopher Petti, Li Xiao, Girish Nagavarapu
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Publication number: 20160133836Abstract: The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.Type: ApplicationFiled: November 11, 2014Publication date: May 12, 2016Applicant: SANDISK 3D LLCInventors: Zhida Lan, Abhijit Bandyopadhyay, Christopher Petti, Li Xiao, Girish Nagavarapu
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Publication number: 20160133325Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.Type: ApplicationFiled: January 14, 2016Publication date: May 12, 2016Applicant: SANDISK 3D LLCInventors: Zhida Lan, Roy E. Scheuerlein, Tong Zhang, Kun Hou, Perumal Ratnam
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Patent number: 9269425Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.Type: GrantFiled: December 10, 2012Date of Patent: February 23, 2016Assignee: SANDISK 3D LLCInventors: Zhida Lan, Roy E. Scheuerlein, Tong Zhang, Kun Hou, Perumal Ratnam
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Patent number: 8879299Abstract: A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode.Type: GrantFiled: July 18, 2012Date of Patent: November 4, 2014Assignee: Sandisk 3D LLCInventors: Kun Hou, Yung-Tin Chen, Zhida Lan, Huiwen Xu
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Patent number: 8861258Abstract: A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.Type: GrantFiled: February 21, 2013Date of Patent: October 14, 2014Assignee: SanDisk 3D LLCInventors: Zhida Lan, Roy E Scheuerlein, Thomas Yan
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Publication number: 20140233299Abstract: A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Applicant: SANDISK 3D LLCInventors: Zhida Lan, Roy E. Scheuerlein, Thomas Yan
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Patent number: 8717803Abstract: The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.Type: GrantFiled: December 9, 2011Date of Patent: May 6, 2014Assignee: Spansion LLCInventors: Manuj Rathor, Suzette K Pangrle, Steven Avanzino, Zhida Lan
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Patent number: 8709891Abstract: Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.Type: GrantFiled: June 14, 2013Date of Patent: April 29, 2014Assignee: 4D-S Ltd.Inventors: Zhida Lan, Dongmin Chen
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Patent number: 8693233Abstract: A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.Type: GrantFiled: January 31, 2012Date of Patent: April 8, 2014Assignee: SanDisk 3D LLCInventors: Roy E Scheuerlein, Henry Chien, Zhida Lan, Yung-Tin Chen
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Publication number: 20130292634Abstract: In some aspects, a memory cell is provided that includes a steering element, a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, and a conductor above the MIM stack. The MIM stack includes a resistance switching element and a top electrode disposed on the resistance switching element, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer between the MIM stack and the conductor. Numerous other aspects are provided.Type: ApplicationFiled: May 7, 2012Publication date: November 7, 2013Inventors: Yung-Tin Chen, Kun Hou, Zhida Lan
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Publication number: 20130279236Abstract: Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Applicant: 4D-S, LTD.Inventors: Zhida Lan, Dongmin Chen
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Publication number: 20130094278Abstract: A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode.Type: ApplicationFiled: July 18, 2012Publication date: April 18, 2013Applicant: SanDisk 3D LLCInventors: Kun Hou, Yung-Tin Chen, Zhida Lan, Huiwen Xu
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Patent number: 8373148Abstract: The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less.Type: GrantFiled: April 26, 2007Date of Patent: February 12, 2013Assignee: Spansion LLCInventors: Zhida Lan, Manuj Rathor, Joffre F. Bernard
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Publication number: 20120195097Abstract: A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material. In a second aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first doped well and located between the two bitlines.Type: ApplicationFiled: April 13, 2012Publication date: August 2, 2012Applicant: 4D-S PTY LTD.Inventor: Zhida LAN
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Publication number: 20120195098Abstract: A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material. In a second aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first doped well and located between the two bitlines.Type: ApplicationFiled: March 29, 2011Publication date: August 2, 2012Applicant: 4D-S PTY LTD.Inventor: Zhida Lan
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Publication number: 20120127779Abstract: A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.Type: ApplicationFiled: January 31, 2012Publication date: May 24, 2012Inventors: Roy E. Scheuerlein, Henry Chien, Zhida Lan, Yung-Tin Chen