Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array, and the array includes N rows and 8M columns. Sub-pixel units in each row are divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit, a fourth sub-pixel unit, a fifth sub-pixel unit, a sixth sub-pixel unit, a seventh sub-pixel unit and an eighth sub-pixel unit which are sequentially in eight adjacent columns along a first direction.

Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array which includes N rows and 4M columns, sub-pixel units in each row is divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit and a fourth sub-pixel unit which are sequentially in four adjacent columns along a first direction.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.

Abstract: An electronic panel, a display device, and a driving method are disclosed. In the electronic panel, each sub-pixel unit includes a light emitting unit, a pixel driving circuit for driving the light emitting unit to emit light, and a sensing circuit for sensing the pixel driving circuit; the gate driving circuit includes N+1 output terminals, and is configured to output gate scanning signals that turn on the N rows of the plurality of sub-pixel units row by row; the pixel driving circuits of the sub-pixel units in a j-th row are connected to a j-th output terminal of the gate driving circuit to receive the gate scanning signal as a scanning driving signal, and the sensing circuits of the sub-pixel units in the j-th row are connected to a (j+1)-th output terminal of the gate driving circuit to receive the gate scanning signal as a sensing driving signal.

Abstract: A display substrate and a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array. At least one sub-pixel includes a first transistor, a second transistor, a third transistor and a storage capacitor. The first electrode of the third transistor is electrically connected to an active layer of the third transistor through a first via hole, and the first electrode of the third transistor is configured to be electrically connected to the light emitting element through a second via hole; the first via hole and the second via hole are at least partially overlapped with each other in a direction perpendicular to the base substrate.

Abstract: The present application discloses a pixel circuit, including a data-input sub-circuit configured to apply a data voltage from the data line to a first node; a reset sub-circuit configured to reset the second node; a driving-control sub-circuit coupled to a first power supply, the first node, and the second node; a power-storage sub-circuit configured to regulate a voltage difference between the first node and the second node; a light-emitting device coupled to the second node and a second power supply; and a sampling sub-circuit coupled to the data line and the second node and being configured to control the data line to connect with the second node for collecting a voltage signal containing information about electrical properties of the driving-control sub-circuit and being used to generating a compensation voltage for compensating any drifts of the electrical properties.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a storage capacitor. The storage capacitor includes a second capacitor electrode, a first capacitor electrode and a third capacitor electrode which are sequentially on the base substrate. The first capacitor electrode has a first capacitor electrode side and a second capacitor electrode side opposite to each other in the second direction, and the second capacitor electrode has a third capacitor electrode side and a fourth capacitor electrode side opposite to each other in the second direction; orthographic projections of the first capacitor electrode side and the second capacitor electrode side on the base substrate are between an orthographic projection of the third capacitor electrode side and an orthographic projection of the fourth capacitor electrode side on the base substrate.

Abstract: An array substrate and a display device are provided. The array substrate includes at least one data line and a plurality of sub-pixel groups arranged in an array along a first direction and a second direction. At least one sub-pixel group includes two rows of sub-pixels, one row of the two rows of sub-pixels includes a first color sub-pixel and a second color sub-pixel, and the other row of the two rows of sub-pixels includes a third color sub-pixel; the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in each sub-pixel group are connected to a same data line of the at least one data line.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-unit and a leakage prevention circuit; the first sub-unit includes a first input circuit and a first output circuit. The first input circuit controls a level of a first node in response to a first input signal, the first output circuit provides an output signal at an output terminal under control of the level of the first node, the leakage prevention circuit is connected to the first node and a first voltage terminal, and controls a level of a leakage prevention node under control of the level of the first node, whereby a conductive path is formed between the leakage prevention node and the first voltage terminal, and a circuit connected between the first node and the leakage prevention node is turned off.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. The display substrate further includes an extension portion protruding from the gate electrode of the first transistor, and the extension portion is extended from the gate electrode of the first transistor in the second direction; the extension portion is at least partially overlapped with the first electrode of the second transistor in a direction perpendicular to the base substrate and is electrically connected with the first electrode of the second transistor; in the first direction, the extension portion has a second side closest to the second capacitor electrode, and the second side is recessed in a direction away from the second capacitor electrode.

Abstract: The present application discloses a shift register, a gate driving circuit and a driving method thereof, and a display apparatus. The shift register includes an input sub-circuit, an output sub-circuit, a reset control sub-circuit, a pull-up node reset sub-circuit, and an output signal reset sub-circuit; the input sub-circuit is configured to pre-charge the pull-up node under the control of a signal input to the first signal input terminal; the output sub-circuit is configured to output, through the signal output terminal, a signal input to the first clock signal input terminal under the control of a potential of the pull-up node; the reset control sub-circuit is configured to control, under the control of a reset signal input to the second signal input terminal, whether the pull-up node reset sub-circuit and the output signal reset sub-circuit operate to reset the pull-up node and the signal output terminal, respectively.

Abstract: The present disclosure provides a display panel and a driving method thereof, and a display apparatus. The display panel includes: a plurality of sub-pixels arranged in an array, a plurality of data lines, and a plurality of compensation detection lines, wherein each data line is coupled with sub-pixels in one column; sub-pixels in every three columns serve as one first sub-pixel group, and each first sub-pixel group corresponds to two compensation detection lines which include a first detection line and a second detection line; and in each first sub-pixel group, sub-pixels in the first column are coupled with the first detection line, sub-pixels in the third column are coupled with the second detection line, and sub-pixels in the second column are alternatively coupled with the first detection line and the second detection line.

Abstract: The present disclosure discloses a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device. With a signal control circuit, a branch control circuit, a cascade signal output circuit and at least two scanning signal output circuits, each shift register can output at least two different scanning signals to correspond to different gate lines in an array substrate. This can reduce the number of shift registers in a gate drive circuit and the space occupied by the gate drive circuit and can achieve an ultra-narrow bezel design, as compared with an existing shift register that can only output one scan signal. Furthermore, as signals of different output control node do not influence each other, the stability of waveforms of the output scanning signals may also be improved, and a difference in the waveforms of the scanning signals is avoided.

Abstract: A display substrate and a fabrication method thereof, a display panel and a display device are provided. The display substrate includes pixels. Each of the pixels includes sub-pixels that emit light of different colors, each of the sub-pixels includes a light emitting element, and at least one of the sub-pixels further includes a color filter. The color filter of the at least one of the sub-pixels covers a portion of a light emitting region of the light emitting element of the at least one of the sub-pixels, and a color of the color filter of the at least one of the sub-pixels is the same as a color of light emitted by the light emitting element of the at least one of the sub-pixels.

Abstract: A thin-film transistor includes a substrate, and a light-shielding layer and an active layer sequentially over the substrate. The light-shielding layer has an accommodating space having a bottom wall and a side wall on an upper surface thereof. An orthographic projection of the active layer on the substrate is contained within an orthographic projection of the accommodating space of the light-shielding layer on the substrate. An upper side of the side wall of the accommodating space of the light-shielding layer has a larger distance to the substrate than a bottom surface, and optionally has an equal or larger distance to the substrate than a top surface, of the active layer. The light-shielding layer can comprise a gate electrode. As such, lights from an underneath and from a lateral side of the thin-film transistor that otherwise reach the active layer can be partially or completely blocked.

Abstract: The present disclosure relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display panel.

Abstract: Embodiments of the present disclosure provide a signal combination circuit, a gate driving unit, a gate driving circuit, and a display device, the signal combination circuit includes a first active level output circuit configured to write an active-level voltage to a driving signal output terminal in a case where a signal provided by a first signal output terminal or a second signal output terminal is at an active level, and a first inactive level output circuit configured to write an inactive-level voltage to the driving signal output terminal in a case where the signals provided by the first signal output terminal and the second signal output terminal are at an inactive level. The signal combination circuit of the embodiments of the disclosure can realize the combination of the single pulse signals output by two shift registers, thereby outputting a double-pulse driving signal.

Abstract: A gate driving circuit includes M levels of shift registers. Each level of shift register includes a first register unit and a second register unit. The first register units of the M levels of shift registers are connected to each other in a cascaded manner, the second register units of the M levels of shift registers are connected to each other in a cascaded manner, and an output end of the first register unit and an output end of the second register unit of each level of shift register are electrically connected to an output end of the level of shift register, where M is a positive integer greater than or equal to 1.

Abstract: The present disclosure provides a gate driving circuit and a driving method, and a display device. The gate driving circuit includes: a plurality of first gate driving units, ith first gate driving unit being configured to output a first gate driving signal to ith row of gate line in a display phase; a plurality of first control modules, mth first control module being configured to control mth second gate driving unit to output a second gate driving signal to mth row of gate line in a vertical blanking phase; nth first control module being configured to control nth second gate driving unit not to output the second gate driving signal in the vertical blanking phase; a plurality of second control modules, kth second control module being configured to control kth second gate driving unit not to output the second gate driving signal in the vertical blanking phase.

Abstract: The present disclosure discloses a shift register, a driving method thereof, a gate drive circuit, an array substrate and a display device. With a signal control circuit, a branch control circuit, a cascade signal output circuit and at least two scan signal output circuits, each shift register can output at least two scan signals to correspond to different gate lines in a display panel. This can reduce the number of shift registers in a gate drive circuit and the space occupied by the gate drive circuit and can achieve an ultra-narrow frame design, as compared with an existing shift register that can only output one scan signal. Moreover, as signals of different output control node do not influence each other, the output stability can also be improved.