Patents by Inventor Zhifeng Wen

Zhifeng Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240098527
    Abstract: This document describes improvements in range and reliability for wireless mesh networks implementing IEEE 802.11 networking technologies. Reducing the number of spatial streams, N, to a lower value at middle and far distance ranges using an optimized rate control algorithm, preemptively trades off a lower throughput limit for a higher link budget. This higher link budget provides longer range and higher RF link reliability by using an N×N spatial diversity of MIMO RF channels for maximizing link budget instead of network throughput.
    Type: Application
    Filed: February 4, 2022
    Publication date: March 21, 2024
    Applicant: Google LLC
    Inventors: Yu Wen, Zhifeng Cai, Srinivasa Kumar Duvvuri, Raymond Reynolds Hayes, Kevin N. Hayes, Der-Woei Wu
  • Patent number: 9047810
    Abstract: The present disclosure provides a circuit for discharging parasitic capacitance in a display panel with common-anode topology having a plurality of light emitters, as well as a circuit for charging parasitic capacitance in a display panel with common-cathode topology. In the common-cathode topology, the circuit includes a three-terminal device having a gate, a source, and a drain, wherein one of the source and the drain is electrically coupled to a common cathode of the light emitters, and a mechanism for controlling the three-terminal device, the mechanism being electrically coupled to the gate. Shortly after a previously selected light emitter is unselected, the mechanism turns on the three-terminal device to form a conductive path between the source and the drain. The mechanism turns off the three-terminal device after a voltage at the common cathode is increased to a predetermined voltage level or after a maximum period of time lapses.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: June 2, 2015
    Assignee: SCT TECHNOLOGY, LTD.
    Inventors: Eric Li, Yutao Chen, Jianxin Xue, Wenjie Yang, Shoulin Li, Chun Lu, Zhifeng Wen, Shean-Yih Chiou, Shang-Kuan Tang, Shahnad Nadershahi
  • Publication number: 20120206430
    Abstract: The present disclosure provides a circuit for discharging parasitic capacitance in a display panel with common-anode topology having a plurality of light emitters, as well as a circuit for charging parasitic capacitance in a display panel with common-cathode topology. In the common-cathode topology, the circuit includes a three-terminal device having a gate, a source, and a drain, wherein one of the source and the drain is electrically coupled to a common cathode of the light emitters, and a mechanism for controlling the three-terminal device, the mechanism being electrically coupled to the gate. Shortly after a previously selected light emitter is unselected, the mechanism turns on the three-terminal device to form a conductive path between the source and the drain. The mechanism turns off the three-terminal device after a voltage at the common cathode is increased to a predetermined voltage level or after a maximum period of time lapses.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 16, 2012
    Applicant: SCT Technology, Ltd.
    Inventors: Eric Li, Chun Lu, Jianxin Xue, Wenjie Yang, Watt Li, Yutao Chen, Zhifeng Wen, Shean-Yih Chiou, Shang-kuan Tang, Nedi Nadershashi