Abstract: The present disclosure provides an innovative method for improving the enzyme activity of an NMN biosynthetic enzyme Nampt, and relates to the technical field of genetic engineering. A mutant protein of the present disclosure is obtained by firstly analyzing a target protein Nampt using two softwares FoldX and DeepDDG, and then predicting multiple key sites influencing the enzyme functions and finally performing the semi-rational design of the enzyme. In the examples of the present disclosure, 10 mutant strains are constructed using the designed primers according to the principle of point mutation, and 8 of the mutants have higher activity than a wild-type strain, in which the NMN yield of the mutant Nampt-V365L is increased by 62%, and the NMN yields of the mutants Nampt-S248A, Nampt-N164L, Nampt-S382M, Nampt-A245T and Nampt-A208G are increased by 34%, 27%, 27%, 22% and 17% respectively.

Abstract: A semiconductor device includes a first terminal, a second terminal positioned away from the first terminal, a first resistive segment coupled between the first terminal and the second terminal, a third terminal positioned away from the first terminal and the second terminal, a second resistive segment coupled between the second terminal and third terminal, a first floating plate disposed physically proximate the first resistive segment and including a first end coupled to one of the first terminal and the second terminal, and a second floating plate disposed physically proximate the second resistive segment and including a first end coupled to one of the second terminal and the third terminal.

Abstract: A semiconductor package structure includes a first redistribution layer, a capacitor structure, and a second redistribution layer. The capacitor structure is disposed over the first redistribution layer and includes a semiconductor substrate, a first capacitor cell, a second capacitor cell, and a through via. The first capacitor cell and the second capacitor cell are disposed over the semiconductor substrate and separated by a first scribe line region. The through via is disposed in the first scribe line region. The second redistribution layer is disposed over the capacitor structure and is electrically coupled to the first redistribution layer through the through via.

Abstract: A semiconductor structure includes a semiconductor substrate, a first capacitor, a first conductive via, a second conductive via, a second capacitor, a first conductive pad, and a second conductive pad. The first capacitor is disposed over the semiconductor substrate. The first conductive via is disposed over the first capacitor. The second conductive via is bonded to the first conductive via. The second capacitor is disposed over the second conductive via. The first conductive pad and the second conductive pad are disposed over the second capacitor and are electrically coupled to the first capacitor and the second capacitor.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer and a test structure. The semiconductor wafer has a substrate having a scribe line area and die areas. The die areas are separated by the scribe line area. The test structure is disposed in the scribe line area. The test structure includes an isolation feature, a first transistor test device, a second transistor test device. The isolation feature is located in the substrate. The first transistor test device and the second transistor test device are disposed on opposite sides of the isolation feature. Channels of the first transistor test device and the second transistor test device have the same conductivity type. A first gate electrode of the first transistor test device and a second gate electrode of the second transistor test device have opposite conductivity types.

Abstract: A semiconductor structure includes a first substrate having a wiring structure, a first semiconductor die disposed on the first substrate, and a multi-terminal capacitor structure disposed on the first substrate. The multi-terminal capacitor includes a second substrate, an insulating layer disposed over the second substrate, a first multi-terminal capacitor disposed over the insulating layer and electrically coupled to the first semiconductor die through the wiring structure, and a second multi-terminal capacitor disposed over the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate.

Abstract: A semiconductor package structure includes a substrate, a composite interposer, and a semiconductor die. The composite interposer is disposed over the substrate and includes a first interposer substrate and a second interposer substrate. The first interposer substrate includes a first conductive via and a first dielectric layer. The second interposer substrate is disposed over the first interposer substrate and includes a second conductive via and a second dielectric layer. The second conductive via is bonded to the first conductive via, and the second dielectric layer is bonded to the first dielectric layer. The semiconductor die is disposed over the composite interposer and is electrically coupled to the first conductive via and the second conductive via.

Abstract: A semiconductor structure includes a first semiconductor substrate, a plurality of first capacitor structures, a first dielectric layer, a second semiconductor substrate, a plurality of second capacitor structures, and a plurality of conductive pillars. The first capacitor structures are disposed in the first semiconductor substrate and arranged side-by-side. The first dielectric layer covers the first capacitor structures. The second semiconductor substrate is disposed over the first dielectric layer. The second capacitor structures are disposed in the second semiconductor substrate and arranged side-by-side. The conductive pillars extend in the first dielectric layer and electrically couple the first capacitor structures to the second capacitor structures.

Abstract: A semiconductor package structure includes a dynamic random access memory (DRAM) die, a capacitor die, and a molding material. The capacitor die is disposed below the DRAM die and includes a plurality of capacitor structures and a plurality of first conductive pillars. The capacitor structures are arranged side-by-side. The first conductive pillars are disposed over the capacitor structures and are electrically coupled to the DRAM die. The molding material surrounds the capacitor die and the DRAM die.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a first dielectric layer, a second dielectric layer and a conductive seal ring structure. The semiconductor substrate has a circuit region and a seal ring region surrounding the circuit region. The first dielectric layer is disposed over the seal ring region, wherein the first dielectric layer has a first dielectric constant. The second dielectric layer is disposed between the semiconductor substrate and the first dielectric layer, wherein the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant. The conductive seal ring structure is disposed in the seal ring region. The conductive seal ring structure includes a first seal ring portion embedded in the first dielectric layer, wherein the first seal ring portion includes first patterns arranged periodically and discontinuously.

Abstract: A semiconductor device includes a first functional block configured to provide a first predetermined function, a second functional block configured to provide a second predetermined function, a first capacitive device, a second capacitive device, a first coupling path, a first switch device and a second switch device. The first capacitive device is disposed physically proximate the first functional block. The second capacitive device is disposed physically proximate the second functional block. The first coupling path includes at least a first connection node connecting to the first functional block. The first switch device is controlled to selectively connect the first capacitive device to the first connection node. The second switch device is controlled to selectively connect the second capacitive device to the second functional block or a second connection node. The second connection node is disposed on the first coupling path and connecting to the first connection node.

Abstract: A semiconductor device includes a substrate and at least one capacitor element on each of opposite surfaces of the substrate. The at least one capacitor element includes a first electrode with a first pad and first terminals connected to the first pad, wherein the first terminals extend away from the substrate, and a second electrode with a second pad and second terminals connected to the second pad, wherein the second terminals extend toward the substrate, wherein the first terminals and the second terminals are staggered and separated by an interlayer dielectric layer.

Abstract: A semiconductor structure includes a first substrate having a wiring structure, a first semiconductor die disposed on the first substrate, and a multi-terminal capacitor structure disposed on the first substrate. The multi-terminal capacitor includes a second substrate, an insulating layer disposed over the second substrate, a first multi-terminal capacitor disposed over the insulating layer and electrically coupled to the first semiconductor die through the wiring structure, and a second multi-terminal capacitor disposed over the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate.

Abstract: A semiconductor device includes a substrate and at least one capacitor element on each of opposite surfaces of the substrate. The at least one capacitor element includes a first electrode with a first pad and first terminals connected to the first pad, wherein the first terminals extend away from the substrate, and a second electrode with a second pad and second terminals connected to the second pad, wherein the second terminals extend toward the substrate, wherein the first terminals and the second terminals are staggered and separated by an interlayer dielectric layer.

Abstract: The present disclosure provides an innovative method for improving the enzyme activity of an NMN biosynthetic enzyme Nampt, and relates to the technical field of genetic engineering. A mutant protein of the present disclosure is obtained by firstly analyzing a target protein Nampt using two softwares FoldX and DeepDDG, and then predicting multiple key sites influencing the enzyme functions and finally performing the semi-rational design of the enzyme. In the examples of the present disclosure, 10 mutant strains are constructed using the designed primers according to the principle of point mutation, and 8 of the mutants have higher activity than a wild-type strain, in which the NMN yield of the mutant Nampt-V365L is increased by 62%, and the NMN yields of the mutants Nampt-S248A, Nampt-N164L, Nampt-S382M, Nampt-A245T and Nampt-A208G are increased by 34%, 27%, 27%, 22% and 17% respectively.

Abstract: A semiconductor package structure includes a substrate, a first redistribution layer, a semiconductor die, a silicon capacitor, and a first bump structure. The first redistribution layer is disposed over the substrate. The semiconductor die is disposed over the first redistribution layer. The silicon capacitor is disposed below the first redistribution layer and is electrically coupled to the semiconductor die, wherein the silicon capacitor includes a semiconductor substrate and a plurality of capacitor cells embedded in the semiconductor substrate. The first bump structure is disposed between the silicon capacitor and the substrate.

Abstract: A semiconductor device includes a first terminal, a second terminal positioned away from the first terminal, a first resistive segment coupled between the first terminal and the second terminal, a third terminal positioned away from the first terminal and the second terminal, a second resistive segment coupled between the second terminal and third terminal, a first floating plate disposed physically proximate the first resistive segment and including a first end coupled to one of the first terminal and the second terminal, and a second floating plate disposed physically proximate the second resistive segment and including a first end coupled to one of the second terminal and the third terminal.

Abstract: Capacitor structures are provided. A capacitor structure includes a first metal line, a second metal line, a plurality of first capacitor cells coupled in parallel between the first metal line and the second metal line, and a plurality of second capacitor cells coupled in parallel between the first metal line and the second metal line. Each of the first capacitor cells includes a first bottom electrode coupled to the first metal line, a first dielectric material over the first bottom electrode, and a first top electrode over the first dielectric material and coupled to the second metal line. Each of the second capacitor cells includes a second bottom electrode coupled to the second metal line, a second dielectric material over the second bottom electrode, and a second top electrode over the second dielectric material and coupled to the first metal line.

Abstract: A semiconductor device includes a substrate and at least one capacitor element. The capacitor element is on the substrate. The capacitor element includes a first electrode with a first pad and first terminals connected to the first pad, wherein the first terminals extend away from the substrate; and a second electrode with a second pad and second terminals connected to the second pad, wherein the second terminals extend toward the substrate, wherein the first terminals and the second terminals are staggered and separated by an interlayer dielectric layer.

Abstract: A semiconductor structure includes a first substrate, a first semiconductor die, a second semiconductor die, and a multi-terminal multi-capacitor structure. The first substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are disposed on the first substrate. The multi-terminal multi-capacitor structure is disposed on the first substrate and includes a second substrate, an insulating layer, a first multi-terminal capacitor, and a second multi-terminal capacitor. The insulating layer is disposed over the second substrate. The first multi-terminal capacitor is disposed over the insulating layer and electrically coupled to the first semiconductor die through the wiring structure.