Abstract: The present disclosure discloses a sintered neodymium-iron-boron magnet and a preparation method thereof. The sintered neodymium-iron-boron magnet includes the following raw materials in mass percentage: 1%-40% of an iron powder or a steel powder with a magnetic induction intensity of more than 1.2 T, not more than 10% of a praseodymium-neodymium metal hydride powder, and a remainder of a neodymium-iron-boron fine powder, wherein the mass percentages of the above raw materials add up to 100%. The preparation method includes: weighing the raw materials in mass percentage; mixing the weighed raw materials uniformly, and then subjecting to magnetic-field press molding, isostatic pressing, sintering and tempering to obtain the sintered neodymium-iron-boron magnet.

Abstract: The present disclosure relates to compositions and methods for treating Williams syndrome (WS), herein identified as a neurodevelopmental oligodendrocyte hypomyelination-associated disease, and to compositions and methods for treatment of other neurodevelopmental myelination abnormality diseases or disorders.

Abstract: Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.

Abstract: Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.

Abstract: Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.