Patents by Inventor Zhigang Hu
Zhigang Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190000341Abstract: A sensor assembly includes a housing and a circuit board assembly. The housing includes a first accommodation cavity, a second accommodation cavity, a first connection portion, a second connection portion, and a third accommodation cavity. The first connection portion is connected to the first accommodation cavity and one end of the third accommodation cavity, and the second connection portion is connected to the second accommodation cavity and the other end of the third accommodation cavity. The circuit board assembly is accommodated within the first accommodation cavity, the second accommodation cavity, the first connection portion, the second connection portion and the third accommodation cavity. The width of the first connection portion and the second connection portion is less than the width of the first accommodation cavity, the second accommodation cavity and the third accommodation cavity.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Inventors: Cong XU, Bingyin WANG, Yangbo LIU, Zhigang HU, Zhonghua LIU
-
Publication number: 20180365275Abstract: A method and apparatus for acquiring people flow information, and a method and apparatus for processing people flow information are provided.Type: ApplicationFiled: June 2, 2016Publication date: December 20, 2018Inventors: Zhigang Hu, Hui Gong, Shiliang Pu
-
Publication number: 20180102771Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal. At least two of the respective delays may have a different duration. The first circuit may also be configured to change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.Type: ApplicationFiled: December 7, 2017Publication date: April 12, 2018Inventors: Zhigang Hu, Hui Yu, Shaokang Wang, Yuan Zhang, Yue Yu
-
Patent number: 9853632Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal and (ii) change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.Type: GrantFiled: January 19, 2016Date of Patent: December 26, 2017Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.Inventors: Zhigang Hu, Hui Yu, Shaokang Wang, Yuan Zhang, Yue Yu
-
Publication number: 20170201243Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal and (ii) change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.Type: ApplicationFiled: January 19, 2016Publication date: July 13, 2017Inventors: Zhigang Hu, Hui Yu, Shaokang Wang, Yuan Zhang, Yue Yu
-
Publication number: 20160269734Abstract: Systems and methods are provided for hybrid video encoding. An example method includes: acquiring image information; extracting a background image based at least in part on the image information; detecting whether the background image is stable; and performing encoding switching between a background-based encoding method and a non-background encoding method based at least in part on the detection.Type: ApplicationFiled: March 9, 2016Publication date: September 15, 2016Inventors: Junyan Tong, Shiliang Pu, Linjie Shen, Cheng Ma, Zhigang Hu, Ye Ren, Hai Yu
-
Patent number: 8798327Abstract: A method and system for people flow statistics is disclosed in the invention, wherein said method comprises: multi-types of classifiers connected in parallel are used to perform the human head detection in the current image, the respective human heads in the current image are determined; the respective determined human heads are tracked to form the human head target movement tracks; and the people flow is counted at the direction of the human head target movement track. It can be seen, a plurality of classifiers connected in parallel are used in the invention, multi-types of human head targets, such as dark colored hair, light colored hair and caps of various colors, and the like, can be detected simultaneously.Type: GrantFiled: February 10, 2010Date of Patent: August 5, 2014Assignee: Hangzhou Hikvision Digital Technology Co., Ltd.Inventors: Zhigang Hu, Yong Zhu, Ye Ren, Weiwei Cai, Yonghua Jia
-
Publication number: 20130070969Abstract: A method and system for people flow statistics is disclosed in the invention, wherein said method comprises: multi-types of classifiers connected in parallel are used to perform the human head detection in the current image, the respective human heads in the current image are determined; the respective determined human heads are tracked to form the human head target movement tracks; and the people flow is counted at the direction of the human head target movement track. It can be seen, a plurality of classifiers connected in parallel are used in the invention, multi-types of human head targets, such as dark colored hair, light colored hair and caps of various colors, and the like, can be detected simultaneously.Type: ApplicationFiled: February 10, 2010Publication date: March 21, 2013Applicant: HANGZHOU HIKVISION DIGITAL TECHNOLOGY CO., LTD.Inventors: Zhigang Hu, Yong Zhu, Ye Ren, Weiwei Cai, Yonghua Jia
-
Patent number: 7930578Abstract: A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.Type: GrantFiled: September 27, 2007Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Zhigang Hu, Hans Jacobson, Prabhakar N. Kudva, Vijayalakshmi Srinivasan, Victor Zyuban
-
Patent number: 7921331Abstract: A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.Type: GrantFiled: June 12, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Pradip Bose, Zhigang Hu, Xiaodong Li, Jude A. Rivers
-
Publication number: 20090089602Abstract: A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.Type: ApplicationFiled: September 27, 2007Publication date: April 2, 2009Inventors: Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Zhigang Hu, Hans Jacobson, Prabhakar N. Kudva, Vijayalakshmi Srinivasan, Victor Zyuban
-
Publication number: 20090083492Abstract: A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.Type: ApplicationFiled: November 17, 2008Publication date: March 26, 2009Applicant: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Zhigang Hu, Jude A. Rivers, John T. Robinson, Xiaowei Shen, Vijayalakshmi Srinivasan
-
Publication number: 20090013207Abstract: A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.Type: ApplicationFiled: August 11, 2008Publication date: January 8, 2009Applicant: International Business Machines CorporationInventors: Pradip Bose, Zhigang Hu, Jude A. Rivers, Jeonghee Shin, Victor Zyuban
-
Patent number: 7472302Abstract: An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased.Type: GrantFiled: October 7, 2005Date of Patent: December 30, 2008Assignees: Agere Systems Inc., The Trustees of Princeton UniversityInventors: Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi
-
Patent number: 7472038Abstract: A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.Type: GrantFiled: April 16, 2007Date of Patent: December 30, 2008Assignee: International Business Machines CorporationInventors: Pradip Bose, Zhigang Hu, Jude A. Rivers, Jeonghee Shin, Victor Zyuban
-
Publication number: 20080313407Abstract: A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is likely to be evicted from the cache. Among a group of highest ranking cache lines in a cache set, the cache line chosen to be replaced is one that provides the lowest latency access to a requesting entity, such as a processor. The distance separating the requesting entity from the memory partition where the cache line is stored most affects access latency.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Inventors: Zhigang Hu, William Robert Reohr
-
Patent number: 7454573Abstract: A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.Type: GrantFiled: January 13, 2005Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Zhigang Hu, Jude A. Rivers, John T. Robinson, Xiaowei Shen, Vijayalakshmi Srinivasan
-
Patent number: 7447923Abstract: A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.Type: GrantFiled: August 19, 2005Date of Patent: November 4, 2008Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Zhigang Hu, Hans Mikael Jacobson, Vijayalakshmi Srinivasan, Victor Zyuban
-
Patent number: 7444544Abstract: A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.Type: GrantFiled: July 14, 2006Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: Pradip Bose, Zhigang Hu, Xiaodong Li, Jude A. Rivers
-
Publication number: 20080256383Abstract: A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.Type: ApplicationFiled: April 16, 2007Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Zhigang Hu, Jude A. Rivers, Jeonghee Shin, Victor Zyuban