Abstract: A data-pattern feedback mechanism is introduced into the peak detection process of an automatic frequency compensation system in a Gaussian Frequency Shift Keying (GFSK) modulated system, providing fast and accurate fine-stage automatic frequency compensation (AFC). Maximum positive and negative peak registers are updated with new values as necessary based on detection during a sequence of identical binary bit values (e.g., during a “00” for detection of maximum negative peak frequency, or during a “11” for detection of maximum positive peak frequency), in a particular data frame. As soon as an initial value is determined for both the maximum positive and negative peak frequencies (e.g., after the first occurrence of a “11” and a “00”, in any order), fine-stage automatic frequency compensation can be initiated. Subsequent adjustments to the VCO of the local oscillator will further refine the frequency offset towards the ideal of zero.

Abstract: A cordless telephone which allows a user to play MP3 digital audio bit stream music, a video game, either alone or with a user of another cordless telephone, using the remote handset of a cordless telephone to control the functions of the MP3 player. The cordless telephone remains usable as a typical cordless telephone with all the features and conveniences of a cordless telephone including, but not limited to, connection of a telephone call between a calling party and a called party, caller ID information, voice messaging features, etc. MP3 digital audio bit stream music may be downloaded from a remote source through, e.g., the Internet and a PC.

Abstract: An improved automatic frequency compensation (AFC) technique and apparatus is provided for piconet applications, e.g., BLUETOOTH™ applications. In particular, the present invention provides an offset normalizer which normalizes frequency offset against maximum deviations. By normalizing the frequency offset, before determination of an adjustment of a local oscillator, the local oscillator adjustment becomes uncorrelated with respect to gain along the receiving path (including in a demodulator). Thus, extremely precise adjustments can be made to the local oscillator in a piconet device to provide extremely precise automatic frequency compensation.

Abstract: A data-pattern feedback mechanism is introduced into the peak detection process of an automatic frequency compensation system in a Gaussian Frequency Shift Keying (GFSK) modulated system, providing fast and accurate fine-stage automatic frequency compensation (AFC). Maximum positive and negative peak registers are updated with new values as necessary based on detection during a sequence of identical binary bit values (e.g., during a “00” for detection of maximum negative peak frequency, or during a “11” for detection of maximum positive peak frequency), in a particular data frame. As soon as an initial value is determined for both the maximum positive and negative peak frequencies (e.g., after the first occurrence of a “11” and a “00”, in any order), fine-stage automatic frequency compensation can be initiated. Subsequent adjustments to the VCO of the local oscillator will further refine the frequency offset towards the ideal of zero.

Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

Abstract: An improved automatic frequency compensation (AFC) technique and apparatus is provided for piconet applications, e.g., BLUETOOTH™ applications. In particular, the present invention provides an offset normalizer which normalizes frequency offset against maximum deviations. By normalizing the frequency offset, before determination of an adjustment of a local oscillator, the local oscillator adjustment becomes uncorrelated with respect to gain along the receiving path (including in a demodulator). Thus, extremely precise adjustments can be made to the local oscillator in a piconet device to provide extremely precise automatic frequency compensation.

Abstract: The present invention provides a baseband RF clock synthesizer having particular use in a BLUETOOTH piconet device, which has the capability of providing simple and accurate calibration of modulation path gain (KMOD) by introducing a dual-loop phase locked loop (PLL) in the RF clock signal synthesizer. The disclosed technique and apparatus controls the maximum frequency deviation by the difference of two locked frequencies, one frequency in each path of the dual-path PLL. Once the PLL is locked within some frequency error, the present technique and apparatus calibrates for the deviation of amplitude of the modulation due to the modulation path. Accordingly, modulation gain (KMOD) calibration is provided by adding an auxiliary loop to a PLL in an RF frequency synthesizer.

Abstract: The present invention provides an architecture for a peripheral device to activate a breakpoint in a processor or other device under emulation. A peripheral breakpoint active signaler allows the peripheral to signal the occurrence of a breakpoint to the processor using a halt or trap line to the processor. This invention provides developers with increased code development capabilities by allowing them to set breakpoints in a peripheral device for the benefit of a processor interfaced with the peripheral to detect when a certain external event has occurred based on the perspective of a peripheral. A breakpoint control register individually enables breakpointing capability of each peripheral with respect to having the capability to halt the processor. Each peripheral has the capability to output a breakpoint request signal to set a bit in a breakpoint status register for readback by the processor, through an external port such as a JTAG test port, or other device.

Abstract: The present invention provides a shared I/O port and a configurable interconnect allowing any of a plurality of cores to access any pin of a shared I/O port. Preferably, one of the plurality of cores is designated as a master core at least with respect to the configuration of the shared I/O port(s), and the remaining cores desiring to gain access to the shared I/O port(s) are designated as non-master or slave cores. It is the responsibility of the master core to reassign chip resources such as the shared I/O port(s) for use by either the master core or by any of the shared cores. Preferably, all shared I/O ports are controlled by default by the master core. The slave cores communicate with the master core through a suitable internal messaging system. If a slave core requires use of a particular I/O pin or I/O port not already configured appropriately for its use, the slave core will send an appropriate message to the master core through the messaging system, e.g., a dual port memory mailbox.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A glitchless clock switch in accordance with the principles of the present invention avoids the need to directly synchronize clock selection signals with the source clock. Instead, clock switching control signals are generated with relation to Finite-State-Machines (FSMs) for each clock signal. Thus, the cycle relationship of the different clock sources do not affect the clock switching process. The FSM for each clock has three states: ON, STOP, and IDLE. During the switching process, each clock signal enters its respective IDLE state. Detection of the ALL_IDLE state is synchronized with a directly derived signal from the newly selected clock. Any glitches in the switching process are isolated to the control of the synchronization of the ALL_IDLE state, which does not affect the output clock signal.

Abstract: A multifunction reset circuit including low power bandgap, a comparator, and an open drain buffer circuit--with the inclusion of four external components (three resistors and one capacitor) to provide undervoltage monitoring, power failure indicating, manual resetting and other reset control conditions to a single integrated circuit terminal, together with hysteresis tolerance.

Abstract: A simple carrier recovery circuit capable of accurately detecting and synchronizing an incoming carrier frequency without the use of a phase locked loop (PLL) is provided. Instead of a PLL, the carrier recovery circuit includes an injection locked oscillator. The injection locked oscillator includes an input for connection to the received modulated signal. The gain of an inverter stage of a amplifier in the injection locked oscillator is modulated by the received modulated signal using an injection transistor connected between the power source and the output of the inverter stage. The gate of the injection transistor receives a signal corresponding to the received modulated signal.

Abstract: An integrated circuit includes a resistor formed in a doped tub located in a semiconductor substrate. A first highly doped resistor contact region extends outward from the associated contact windows towards a second highly doped resistor contact region. The extent of the underlying tub region that lies between the highly doped tub contact regions largely determines the resistance value. The size and geometry of the highly doped resistor contact regions, and hence the resistance of the resistor, is typically determined by the same mask that defines the thin oxide regions of field effect transistors formed on the IC. In a typical application, the resistor is connected between an output buffer and a bondpad. A multiplicity of output buffers on an IC chip may each connect to corresponding bondpads using a multiplicity of the inventive resistors, which may have the same, or alternatively differing, resistance values.