Abstract: The present disclosure provides a chip packaging method and a chip packaging structure. The chip packaging method includes: providing an encapsulated grain and a packaging substrate, the encapsulated grain including a first hybrid bonding structure; wherein the packaging substrate includes a front side and a back side opposite to each other; a second hybrid bonding structure is formed on the front side of the packaging substrate and a connection pin is formed on the back side of the packing substrate; the second hybrid bonding structure and the connection pin are electrically connected through a third connecting metal column penetrating the packaging substrate; and bonding together the first hybrid bonding structure of the encapsulated grain and the second hybrid bonding structure of the packaging substrate by medium-to-medium and metal-to-metal aligned bonding such that the encapsulated grain is bonded to the packaging substrate.

Abstract: Systems, computer-implemented methods, and instructions encoded in machine-accessible storage media are provided for determining manufacturability of an integrated circuit layout. A computer-implemented method includes receiving a layout describing the integrated circuit to be manufactured by a semiconductor manufacturing process. The method also includes generating a differentiable manufacturability parameter as an output of a machine learning model using the layout, the machine learning model being trained to generate the differentiable manufacturability parameter. The differentiable manufacturability parameter describes the manufacturability of the integrated circuit by the semiconductor manufacturing process.

Abstract: A computer-implemented method for integrated circuit routing is described. The computer-implemented method comprising receiving a description of interconnected terminals of an integrated circuit with a wiring route electrically coupling the interconnected terminals and configuring a simulated environment defined via a plurality of voxels based on the description. The individual voxels included in the plurality of voxels each correspond to a spatial representation for a corresponding region of a layout associated with the integrated circuit. The computer-implemented method further includes determining local contributions of the individual voxels to a characteristic metric of the integrated circuit based on an electromagnetic simulation of the integrated circuit and revising the wiring route based on the local contributions of the individual voxels.

Abstract: Embodiments of a system and method for generating integrated circuit layouts are described herein. A computer implemented method for generating integrated circuit layouts includes receiving a first layout for an integrated circuit, segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout, identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit, generating a transformation of the non-compliant patch using a machine learning model, and generating a second layout using the transformation and the first layout, where the second layout is compliant with the design rule.

Abstract: Embodiments of a system and method for generating integrated circuit layouts are described herein. A computer implemented method for generating integrated circuit layouts includes receiving a first layout for an integrated circuit, segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout, identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit, generating a transformation of the non-compliant patch using a machine learning model, and generating a second layout using the transformation and the first layout, where the second layout is compliant with the design rule.

Abstract: The invention relates to an airborne laser scanner configured to be arranged on an aircraft for surveying a target along a flight path, wherein the airborne laser scanner comprises an emitter configured for emitting a plurality of consecutive laser pulses towards the ground surface, at least one optical element configured for deflecting the laser pulses along pulse paths towards the target, a motor configured for moving the optical element to cause a periodically repeating movement of the pulse paths, a receiver configured for receiving the laser pulses backscattered from the target, and a computer configured for controlling the emitter, the motor, and the receiver, determining directions of the pulse paths, and triggering the emitter to emit the laser pulses.

Abstract: A multiple-pulses-in-air (MPiA) laser scanning system, wherein the MPiA problem is addressed in that an MPiA assignment of return pulses to send pulses of a laser scanner is based on range tracking and range probing at intermittent points in time. Each range probing comprises a time-of-flight arrangement which is constructed to be free of the MPiA problem. The invention further relates to an MPiA laser scanning system, wherein an MPiA ambiguity within a time series of return pulses, is converted into 3D point cloud space, which provides additional information from the spatial neighborhood of the points in question to enable MPiA disambiguation.

Abstract: Provided is a cutting tool that includes a cutting head, a frame, a working table, a guiding rail assembly, and a fence. The cutting head is configured to perform a cutting function. The frame is configured to support the cutting head. The working table is configured to place an object to be cut. The guiding rail assembly is configured to enable the working table to slide along a first straight line relative to the frame. The fence is mounted to the working table, includes at least one fence surface extending in a direction perpendicular to the first straight line. The cutting tool enables a workpiece to be cut to be stably placed on the working table during a cutting operation.

Abstract: A multiple-pulses-in-air (MPiA) laser scanning system, wherein the MPiA problem is addressed in that an MPiA assignment of return pulses to send pulses of a laser scanner is based on range tracking and range probing at intermittent points in time. Each range probing comprises a time-of-flight arrangement which is constructed to be free of the MPiA problem. The invention further relates to an MPiA laser scanning system, wherein an MPiA ambiguity within a time series of return pulses, is converted into 3D point cloud space, which provides additional information from the spatial neighborhood of the points in question to enable MPiA disambiguation.

Abstract: Provided is a cutting tool that includes a cutting head, a frame, a working table, a guiding rail assembly, and a fence. The cutting head is configured to perform a cutting function. The frame is configured to support the cutting head. The working table is configured to place an object to be cut. The guiding rail assembly is configured to enable the working table to slide along a first straight line relative to the frame. The fence is mounted to the working table, includes at least one fence surface extending in a direction perpendicular to the first straight line. The cutting tool enables a workpiece to be cut to be stably placed on the working table during a cutting operation.

Abstract: Disclosed is a crosshead component of a large diesel engine. The crosshead component consists of a crosshead pin (1), slide blocks (2), wear-resisting plates (3), sealing covers (4), and a sleeve (5), and has a structure with H-shaped cross and longitudinal sections. The crosshead pin (1) is a cylinder provided with petal-shaped through holes. The slide blocks (2) are respectively fitted on and connected to outer circles of left and right ends of the crosshead pin (1). The sleeve (5) is inserted in and connected to the petal-shaped through holes (112) of the crosshead pin (1) to form oil inlet/return way cavities. Left and right end surfaces of the crosshead pin (1) are respectively connected to the sealing covers (4) for sealing the oil way cavities. Front and back ends of the slide blocks (2) are respectively connected to the wear-resisting plates (3). The crosshead component has excellent interchangeability, economy and convenience.

Abstract: Disclosed is a crosshead component of a large diesel engine. The crosshead component consists of a crosshead pin (1), slide blocks (2), wear-resisting plates (3), sealing covers (4), and a sleeve (5), and has a structure with H-shaped cross and longitudinal sections. The crosshead pin (1) is a cylinder provided with petal-shaped through holes. The slide blocks (2) are respectively fitted on and connected to outer circles of left and right ends of the crosshead pin (1). The sleeve (5) is inserted in and connected to the petal-shaped through holes (112) of the crosshead pin (1) to form oil inlet/return way cavities. Left and right end surfaces of the crosshead pin (1) are respectively connected to the sealing covers (4) for sealing the oil way cavities. Front and back ends of the slide blocks (2) are respectively connected to the wear-resisting plates (3). The crosshead component has excellent interchangeability, economy and convenience.

Abstract: A method for performing optical proximity correction with process variations considerations is disclosed. The maximum aerial gradient direction for a control point associated with an edge is initially determined. Then, a variational edge placement error E?along the maximum aerial image intensity gradient direction of the control point is calculated. A determination is made whether or not |CE·n| is equal to or greater than a manufacturing grid, where n is the direction perpendicular to a segment pointing outward, and C is a constant. If |CE·n| is equal to or greater than a manufacturing grid, the edge is moved by ?CE·n.

Abstract: A method for performing global routing on an integrated circuit design is disclosed. The integrated circuit design is initially divided into multiple G-cells. The G-cells are interconnected by a set of nets. The set of nets is then decomposed into corresponding wires. The wires are prerouted to interconnect the G-cells. BoxRouting is performed on the wires until all the wires are routed. Finally, postrouting is performed on the wires.

Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Abstract: A method for performing optical proximity correction with process variations considerations is disclosed. The maximum aerial gradient direction for a control point associated with an edge is initially determined. Then, a variational edge placement error E along the maximum aerial image intensity gradient direction of the control point is calculated. A determination is made whether or not |CE·n| is equal or greater than a manufacturing grid, where n is the direction perpendicular to a segment pointing outward, and C is a constant. If |CE·n| is equal or greater than a manufacturing grid, moving said edge by ?CE·n.

Abstract: A method for performing global routing on an integrated circuit design is disclosed. The integrated circuit design is initially divided into multiple G-cells. The G-cells are interconnected by a set of nets. The set of nets is then decomposed into corresponding wires. The wires are prerouted to interconnect the G-cells. BoxRouting is performed on the wires until all the wires are routed. Finally, postrouting is performed on the wires.

Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.