Abstract: This invention relates to a method for making 32-bit addressing of SV data by utilizing FPGA, which may be applied to processing digital sampling data in an equipment of an intelligent substation. Specifically, the method includes the following steps: FPGA receiving naked SV data packages generated based on IEEE802.3 standard; analyzing data structure of Ethernet frame; based on characteristics of the Ethernet frame of the SV data, the SV data of the network byte sequence being reorganized by utilizing ASN.1 coding rules, so that the SV data being converted into a data that can be directly accessed by 32-bit addressing processors. As a result, SV data decoding efficiency is improved greatly. This invention may make the decoding efficiency of 32-bit addressing processor improved by 5-10 times, thus solve problem of declined efficiency due to processing network byte order by splitting and reorganization.

Abstract: The invention discloses a sensor pad for intelligent wireless alarm, comprising a sensor pad and an alarm device. The sensor pad is provided with contact layers, conductor layers, an elastic isolation layer and a controller; through holes are formed in the elastic isolation layer; the conductor layers are separately arranged on upper and lower sides of the elastic isolation layer; the controller is provided with a non-volatile memory module and Bluetooth module or high-frequency wireless transmitting module; the controller is fixedly connected with conductor layers; the conductor layers, elastic isolation layer and controller are wrapped and fixed by contact layers; the alarm device is provided with a switch, control panel, microphone, loudspeaker and function buttons; and a Bluetooth module or high-frequency wireless receiving module matched with the sensor pad is arranged on the control panel, and the switch, microphone, loudspeaker and function buttons are connected with the control panel.

Abstract: This invention relates to a method for making 32-bit addressing of SV data by utilizing FPGA, which may be applied to processing digital sampling data in an equipment of an intelligent substation. Specifically, the method includes the following steps: FPGA receiving naked SV data packages generated based on IEEE802.3 standard; analyzing data structure of Ethernet frame; based on characteristics of the Ethernet frame of the SV data, the SV data of the network byte sequence being reorganized by utilizing ASN.1 coding rules, so that the SV data being converted into a data that can be directly accessed by 32-bit addressing processors. As a result, SV data decoding efficiency is improved greatly. This invention may make the decoding efficiency of 32-bit addressing processor improved by 5-10 times, thus solve problem of declined efficiency due to processing network byte order by splitting and reorganization.