Abstract: A resonator for testing, a method for manufacturing a resonator for testing, and a method for testing a resonator are provided. The resonator for testing includes: a testing substrate, a testing bottom electrode, a testing piezoelectric layer, a testing top electrode, at least one first testing electrode, and at least one second testing electrode. The first testing electrode is connected to the testing bottom electrode, the second testing electrode is connected to the testing top electrode, a spacing region is arranged between the first testing electrode and the second testing electrode, and a thickness between the testing piezoelectric layer and at least one of the first testing electrode and the second testing electrode is greater than a predetermined thickness to insulate the first testing electrode and the second testing electrode.

Abstract: A resonator for testing, a method for manufacturing a resonator for testing, and a method for testing a resonator are provided. The resonator for testing includes: a testing substrate, a testing bottom electrode, a testing piezoelectric layer, a testing top electrode, at least one first testing electrode, and at least one second testing electrode. The first testing electrode is connected to the testing bottom electrode, the second testing electrode is connected to the testing top electrode, a spacing region is arranged between the first testing electrode and the second testing electrode, and a thickness between the testing piezoelectric layer and at least one of the first testing electrode and the second testing electrode is greater than a predetermined thickness to insulate the first testing electrode and the second testing electrode.

Abstract: A semiconductor device including a first functional module arranged on a first substrate and having a chip, an electrical connection component and a sealing ring, where the sealing ring surrounds the chip, and the chip is electrically connected to the electrical connection component; a second functional module having a packaging substrate, where the packaging substrate includes at least two metal layers and a dielectrical layer between the metal layers; a third functional module having multiple redistribution lines and multiple micro through holes for electrical connection between the first functional module and the second functional module, where the electrical connection component in the first functional module is electrically connected to the third functional module; and a second substrate, where the second substrate is sealed with the first substrate.

Abstract: Circuits, devices and methods related to adjustment of input signal for compensation of amplifier. In some embodiments, a control system for an amplifier can include a control circuit configured to provide a control signal based on an operating condition associated with the amplifier. The control system can further include a power adjustment component implemented along an input path associated with the amplifier and configured to adjust power of a signal to be amplified by the amplifier.

Abstract: Dynamic error vector magnitude correction for radio-frequency amplifiers. In some embodiments, a radio-frequency amplification system can include an amplifier configured to receive an input signal through an input path and generate an amplified signal, a power adjustment component implemented along the input path and configured to adjust power of the input signal, and a control circuit configured to provide a control signal to the power adjustment component based on an operating condition associated with the amplifier, such that an impact of the operating condition on the amplifier is compensated by the adjusted power of the input signal.

Abstract: Dynamic error vector magnitude correction for radio-frequency amplifiers. In some embodiments, a radio-frequency amplification system can include an amplifier configured to receive an input signal through an input path and generate an amplified signal, a power adjustment component implemented along the input path and configured to adjust power of the input signal, and a control circuit configured to provide a control signal to the power adjustment component based on an operating condition associated with the amplifier, such that an impact of the operating condition on the amplifier is compensated by the adjusted power of the input signal.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: A signal handler providing high linearity in a small size, applicable across wide operating frequencies and bandwidths, while also adapted to preferred integrated circuit (IC) and printed circuit board technologies. In one implementation, a signal handling apparatus includes an input impedance transformer for receiving an input signal and matching an internal apparatus impedance, a splitter for providing N split signals, a number of signal processing circuits for processing the N split signals, a combiner for combining the N split signals into a combined signal, and output impedance transformer for receiving the combined signal and for matching the internal apparatus impedance to an output impedance of the apparatus. The apparatus may provide filtering, duplexing and other radio frequency signal processing functions. A tunable duplexer may be implemented using a vector inductor and tunable capacitor array with frequency dependent impedance transformers.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: A multi-stage signal handling circuit. Operating as a combiner or splitter, first stage transformers match low input impedance at a first set of differential terminals, and second stage transformers match expected higher impedance at second terminal(s). Transformer windings are mirror image, vertically aligned, meandering conductive tracks disposed on opposite sides of a PCB. Air columns above or below the conductive tracks reduce ground plane effects. A capacitor provided across the differential input terminals of each transformer is chosen to further match the power amplifier output, including consideration of inherent inductance presented by the circuit tracks and vias between transformer sections.