Abstract: A display panel and a manufacturing method thereof are disclosed. The display panel includes a plurality of scan lines parallel to one another, a plurality of data lines parallel to one another, a common electrode, and a plurality of connection lines. The scan lines and the data lines are disposed in different layers and perpendicular to each other. A loop of a second metal layer is disposed in a non-display region in the layer in which the data lines are disposed. A plurality of connection lines are disposed to be parallel to the data lines. A plurality of protrusion structures are disposed on the scan lines at intervals along a first direction.

Abstract: A display panel and a method of manufacturing the display panel are provided. The display panel includes a substrate and a transistor layer. The transistor array layer includes a first metal layer disposed above the substrate. The first metal layer includes a gate, a second metal layer disposed above the first metal layer. The second metal layer includes a source, a drain, and a metal trace, and at least one repair part disposed on both sides of the metal trace. The repair part and the metal trace are configured to form a signal trace.

Abstract: A display panel and a manufacturing method thereof are disclosed. The display panel includes a plurality of scan lines parallel to one another, a plurality of data lines parallel to one another, a common electrode, and a plurality of connection lines. The scan lines and the data lines are disposed in different layers and perpendicular to each other. A loop of a second metal layer is disposed in a non-display region in the layer in which the data lines are disposed. A plurality of connection lines are disposed to be parallel to the data lines. A plurality of protrusion structures are disposed on the scan lines at intervals along a first direction.

Abstract: A fan-out wire structure, a display panel, and a display device are provided. The fan-out wire structure includes a first wiring layer, a second wiring layer, and a plurality of fan-out wires. The fan-out wires include a plurality of first fan-out wires and a plurality of second fan-out wires. The first fan-out wires are disposed in the first wiring layer. The fan-out wires are disposed in the second wiring layer. Each of the first fan-out wires is provided with a first impedance unit. Each of the second fan-out wires is provided with a second impedance unit.

Abstract: An array substrate and a display panel are provided. The array substrate includes a first region and a second region. The first region corresponds to a display region of the display panel. The second region corresponds a non-display region of the display panel. The second region includes a substrate and an electrically conductive line formed on the substrate. The second region further includes at least one metal pattern formed between the substrate and the electrically conductive line.

Abstract: An array substrate and a display panel are provided. The array substrate includes a first region and a second region. The first region corresponds to a display region of the display panel. The second region corresponds a non-display region of the display panel. The second region includes a substrate and an electrically conductive line formed on the substrate. The second region further includes at least one metal pattern formed between the substrate and the electrically conductive line.

Abstract: An array substrate, a display panel, and a display device are provided. The array substrate includes a wiring region and a thin film transistor (TFT) device functional region. The wiring region includes a gate electrode layer, a dielectric layer disposed on the gate electrode layer, and a data wire layer disposed on the dielectric layer. A plurality of via holes are defined on the dielectric layer. The data wire layer is connected to the gate electrode layer through the plurality of via holes. A data wire formed from the data wire layer and a gate wire formed from the gate wire electrode layer constitute a parallel connection structure at positions of the plurality of via holes.

Abstract: An integrated circuit pin is provided. The integrated circuit pin includes a glass substrate, a buffer layer above the glass substrate, a gate insulating layer above the buffer layer, a first metal layer above the gate insulating layer, a second metal layer above the first metal layer, a first insulating layer above the second metal layer, a second insulating layer above the first insulating layer, a bottom indium tin oxide (BITO) above the second insulating layer, and a top indium tin oxide covering the BITO. The BITO further extends downwardly along the inner wall of a through-hole penetrating through the first and second insulating layers such that the BITO is connected to the second metal layer. An in-cell touch panel is also provided. According to the disclosure, the thickness of the conductive layer can be increased. The anti-external interference and the drop reliability of ITP products can be enhanced.

Abstract: An array substrate used for a touch display screen is provided. The array substrate comprises a substrate; a polysilicon layer disposed on the substrate; a dielectric layer disposed on the polysilicon layer and the substrate; a touch line, a connecting line and data line arranged sequentially at intervals on the dielectric layer; a planarization layer covering the connecting line and data line; wherein a first through-hole and second through-hole arranged sequentially at intervals are formed on planarization layer, the touch line is facing and exposed from first through-hole; a portion of the connecting line is facing and exposed from second through-hole; a source and drain in contact with a portion of the surface of polysilicon layer are formed in dielectric layer arranged at intervals, the drain and source are respectively connected with the connecting line and data line, and the first through-hole is completely misplaced with the second through-hole.

Abstract: The present invention relates to a display panel technology field. An array substrate comprises a first metal layer, a buffer layer, a semiconductor layer, an insulating layer, a scanning metal layer, an inter layer dielectric, and a second metal layer that are sequentially stacked on a glass substrate along a first direction, and a first pixel set and a second pixel set that are arranged alternately along a second direction; and a first conductive path sequentially connecting the first pixel set and a second conductive path sequentially connecting the second pixel set. The first conductive path and the second conductive path change lines alternately in the first metal layer and the second metal layer, such that the first pixel set and the second pixel set are sequentially connected in series. With the array substrate of the present invention, the metal layer for changing line can be eliminated.

Abstract: An integrated circuit pin is provided. The integrated circuit pin includes a glass substrate, a buffer layer above the glass substrate, a gate insulating layer above the buffer layer, a first metal layer above the gate insulating layer, a second metal layer above the first metal layer, a first insulating layer above the second metal layer, a second insulating layer above the first insulating layer, a bottom indium tin oxide (BITO) above the second insulating layer, and a top indium tin oxide covering the BITO. The BITO further extends downwardly along the inner wall of a through-hole penetrating through the first and second insulating layers such that the BITO is connected to the second metal layer. An in-cell touch panel is also provided. According to the disclosure, the thickness of the conductive layer can be increased. The anti-external interference and the drop reliability of ITP products can be enhanced.

Abstract: An array substrate manufacturing method, an array substrate, a display panel and a display device are disclosed. The array substrate comprises a planarization layer and common touch electrodes located on the planarization layer, wherein the planarization layer is provided with a plurality of convex areas and a plurality of concave areas, and the common touch electrodes are disposed in the concave areas. In this way, abnormal display of the display panel caused by gap inconsistencies may be effectively avoided.

Abstract: The present invention discloses a touch liquid crystal display panel. The panel includes: a lower substrate, wherein an inner surface of the lower substrate is provided with a first and a second common electrode regions, and a spacer region located between the first and the second common electrode regions; a dielectric insulation layer covering on the first and the second common electrode regions and the entire spacer region; and an upper substrate opposite to the lower substrate, wherein an inner surface of the upper substrate is provided with a first and a second spacers, and the first spacer is pressed against the dielectric insulation layer corresponding to the first common electrode region and/or the second common electrode regions, and the second spacer is pressed against the dielectric insulation layer corresponding to the spacer region; wherein a height of the second spacer is greater than a height of the first spacer.

Abstract: The present invention relates to a display panel technology field. An array substrate comprises a first metal layer, a buffer layer, a semiconductor layer, an insulating layer, a scanning metal layer, an inter layer dielectric, and a second metal layer that are sequentially stacked on a glass substrate along a first direction, and a first pixel set and a second pixel set that are arranged alternately along a second direction; and a first conductive path sequentially connecting the first pixel set and a second conductive path sequentially connecting the second pixel set. The first conductive path and the second conductive path change lines alternately in the first metal layer and the second metal layer, such that the first pixel set and the second pixel set are sequentially connected in series. With the array substrate of the present invention, the metal layer for changing line can be eliminated.

Abstract: An array substrate used for a touch display screen is provided.