Abstract: Panoramic imaging systems and techniques are disclosed. In one aspect, a technique for automatic detecting and tracking of a foreground object includes the steps of: receiving a first set of raw images in an image sequence captured by a panoramic imaging system; stitching, by the panoramic imaging system, the first set of raw images to generate a panoramic image; detecting, by the panoramic imaging system, a foreground object in the panoramic image; tracking, by the panoramic imaging system, a movement of the foreground object in the image sequence; and generating, by the panoramic imaging system, a panoramic video based on the image sequence with tracking the movement of the foreground object.

Abstract: According to embodiments of the present invention, a sensing device is provided. The sensing device includes a sensor arrangement including an optical fiber, and at least one spacer element arranged adjacent to the optical fiber, wherein the optical fiber and the at least one spacer element are adapted to cooperate to receive a force applied to the sensor arrangement to modulate an optical signal propagating in the optical fiber. According to further embodiments of the present invention, a method for sensing a force is also provided.

Abstract: Features are disclosed relating to determining an activity in which a user is (or has been) engaged. One such activity is the taking of steps (e.g., walking or running). Some embodiments described herein are directed to accurate detection and counting of steps made by a user wearing a device with step-detection functionality. The accurate step counting can be facilitated by detecting signatures of certain activities, and determining whether to count steps based on an analysis of acceleration data over various intervals and moving windows of time.

Abstract: An apparatus, methods and a system for cuffless blood pressure monitoring are provided. The system includes an optical BCG sensor, a PPG sensor, a transceiver and a signal processing device. The BCG sensor optically couples to the subject, acquires BCG signals from the subject, and optically transmits the subject's BCG signals. The PPG sensor optically couples to the subject for acquiring PPG signals from the subject and optically transmits the acquired subject's PPG signals. The transceiver is coupled to the BCG sensor and the PPG sensor for receiving the BCG signals and the PPG signals and generating a BCG electronic signal from the subject's BCG signals and a PPG electronic signal from the subject's PPG signals.

Abstract: A method for fabricating an NMOS transistor includes providing a substrate; forming a gate dielectric layer structure on the substrate and forming a gate electrode on the gate dielectric layer structure. The method further includes performing a fluorine ion implantation below the gate dielectric layer and an annealing process in an atmosphere comprising hydrogen or hydrogen plasma. The method also includes forming a source region and a drain region on both sides of the gate electrode before or after the fluorine ion implantation.

Abstract: A method for fabricating an NMOS transistor includes providing a substrate; forming a gate dielectric layer structure on the substrate and forming a gate electrode on the gate dielectric layer structure. The method further includes performing a fluorine ion implantation below the gate dielectric layer and an annealing process in an atmosphere comprising hydrogen or hydrogen plasma. The method also includes forming a source region and a drain region on both sides of the gate electrode before or after the fluorine ion implantation.

Abstract: A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

Abstract: Fiber sensors formed on side-polished fiber coupling ports based on evanescent coupling are described. Such sensors may be configured to measure various materials and may be used to form multi-phase sensing devices. A Bragg grating may be implemented in such sensors to form reflective fiber sensors.

Abstract: Waveguide sensors having a side-polished coupling port at the waveguide cladding to sense a material based on material-specific optical attenuation by evanescent coupling at the coupling port.

Abstract: Fiber sensors formed on side-polished fiber coupling ports based on evanescent coupling. Such sensors may be configured to measure various materials and may be used to form multi-phase sensing devices.

Abstract: Fiber sensors formed on side-polished fiber coupling ports based on evanescent coupling are described. Such sensors may be configured to measure various materials and may be used to form multi-phase sensing devices. A Bragg grating may be implemented in such sensors to form reflective fiber sensors.

Abstract: Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

Abstract: A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

Abstract: Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

Abstract: A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

Abstract: Adjustable filters formed in fibers or waveguides based on evanescent coupling, where a coupling layer is formed between a waveguide overlay and a side-polished coupling port on the fiber or waveguide. A control mechanism may be provided to adjust a property of at least one of the waveguide overlay and the coupling layer to adjust the output of the filter.

Abstract: A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.

Abstract: A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

Abstract: A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.