Abstract: An integrator circuit cancels a DC offset component related to an average DC value of a burst mode input signal from the output of an amplifier. The integrator circuit outputs an average DC value of the input signal in a response time that is shorter than the preamble of a burst mode signal. The integrator output signal remains stable within selected amplitude limits for a length of time corresponding to the data portion of a burst mode signal. A transimpedance amplifier embodiment of the invention comprises a TIA gain stage, an integrator, and a voltage-controlled current course. Other embodiments comprise an amplifier for converting single-ended input signals to differential output signals, an amplifier for differential output offset cancellation, a monolithic semiconductor integrated circuit die, and a packaged semiconductor integrated circuit device.

Abstract: An integrator circuit cancels a DC offset component related to an average DC value of a burst mode input signal from the output of an amplifier. The integrator circuit outputs an average DC value of the input signal in a response time that is shorter than the preamble of a burst mode signal. The integrator output signal remains stable within selected amplitude limits for a length of time corresponding to the data portion of a burst mode signal. A transimpedance amplifier embodiment of the invention comprises a TIA gain stage, an integrator, and a voltage-controlled current course. Other embodiments comprise an amplifier for converting single-ended input signals to differential output signals, an amplifier for differential output offset cancellation, a monolithic semiconductor integrated circuit die, and a packaged semiconductor integrated circuit device.

Abstract: A peak detector for implementation in a monolithic integrated circuit includes one or more Miller capacitors and one or more transistors for selectively setting large RC time constant values only with components included in the integrated circuit's die. Neither resistors nor capacitors located outside the integrated circuit are used for setting a selected value of a time constant. Some embodiments of the invention include diodes for compensation of amplifier leakage current in the peak detector, thereby increasing a maximum value of a time constant that can be implemented in an integrated circuit. A peak detector in accord with an embodiment of the invention may optionally be configured for either single-ended or differential operation.

Abstract: A peak detector for implementation in a monolithic integrated circuit includes one or more Miller capacitors and one or more transistors for selectively setting large RC time constant values only with components included in the integrated circuit's die. Neither resistors nor capacitors located outside the integrated circuit are used for setting a selected value of a time constant. Some embodiments of the invention include diodes for compensation of amplifier leakage current in the peak detector, thereby increasing a maximum value of a time constant that can be implemented in an integrated circuit. A peak detector in accord with an embodiment of the invention may optionally be configured for either single-ended or differential operation.

Abstract: Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector, such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data.

Abstract: Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector, such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data.