Abstract: A display device includes a pixel array including M rows of pixel units, M scanning lines, a first drive module, and a second drive module. An Nth scanning line is connected to the pixel units in an Nth row and the pixel units (11) in an (N+2)th row. One of the first drive module and the second drive module is connected to the scanning line connected to the pixel units in an odd row and is configured to supply, via the scanning line, a scanning signal and a reset signal to the pixel units in the odd row, and the other of the drive modules is connected to the scanning line connected to the pixel units in an even row and is configured to supply, via the scanning line, a scanning signal and a reset signal to the pixel units in the even row.

Abstract: The present disclosure relates to a pixel driving circuit for switching display resolution, a driving method thereof, and a display apparatus. The pixel driving circuit comprises: r first data lines and k second data lines, each of the first data lines has a first switch provided thereon, and is connected to at least one of the k second data lines through at least one second switch respectively, and the first switch and the second switch are connected to a signal control unit which is configured to control the first switch to be turned on and the second switch to be turned off when display is to be performed at a first resolution, and control the first switch to be turned off and the second switch to be turned on when display is to be performed at a second resolution.

Abstract: The embodiments of the present disclosure provide a partition-based gate driving method and apparatus and a gate driving unit, and relates to the field of display technology. In the embodiments of the present disclosure, the partition-based gate driving method comprises: generating a control signal according to an acquired human eye observation partition; generating a second clock signal or a third clock signal according to the control signal; and controlling a second output signal according to the second clock signal or controlling a third output signal according to the third clock signal, thereby controlling the display area to be displayed by partitions.

Abstract: The present application discloses a reflective display panel, a driving method thereof, a control method of a pixel unit and a reflective display device. The reflective display panel comprises: a base substrate, a reflective layer, first and second electrode layers, wherein the first electrode layer is on a side of the reflective layer distal to the base substrate, the second electrode layer is on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, materials of the first and second electrode layers are each an electro-optic material, and orthogonal projections of the second and first electrode layers on the base substrate have overlapping areas corresponding to the pixel units.

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

Abstract: The present invention discloses a gate driver on array circuit and a driving method thereof, and a display device. The gate driver on array circuit comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive in a first working state which is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive in a second working state which is a state in which a defect occurs in the first gate driver on array sub-circuit. The present invention improves the yield rate of the gate driver on array circuit.

Abstract: The present disclosure relates to a pixel driving circuit, a driving method thereof, and a display apparatus, to realize switch between resolutions of the display apparatus which is driven by the pixel driving circuit. The pixel driving circuit comprises: r first data lines and k second data lines, each of the first data lines has a first switch unit provided thereon, and is connected to q second data lines through a second switch unit, and the first switch unit and the second switch unit are connected to a signal control unit respectively; and the signal control unit is configured to control the first switch unit to be turned on and the second switch unit to be turned off when display is to be performed at a first resolution, and control the first switch unit to be turned off and the second switch unit to be turned on when display is to be performed at a second resolution, wherein the first resolution is greater than the second resolution.

Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

Abstract: The embodiments of the present disclosure provide a partition-based gate driving method and apparatus and a gate driving unit, and relates to the field of display technology. In the embodiments of the present disclosure, the partition-based gate driving method comprises: generating a control signal according to an acquired human eye observation partition; generating a second clock signal or a third clock signal according to the control signal; and controlling a second output signal according to the second clock signal or controlling a third output signal according to the third clock signal, thereby controlling the display area to be displayed by partitions.

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

Abstract: The present application discloses a reflective display panel, a driving method thereof, a control method of a pixel unit and a reflective display device. The reflective display panel comprises: a base substrate, a reflective layer, first and second electrode layers, wherein the first electrode layer is on a side of the reflective layer distal to the base substrate, the second electrode layer is on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, materials of the first and second electrode layers are each an electro-optic material, and orthogonal projections of the second and first electrode layers on the base substrate have overlapping areas corresponding to the pixel units.

Abstract: The present invention discloses a gate driver on array circuit and a driving method thereof, and a display device. The gate driver on array circuit comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive in a first working state which is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive in a second working state which is a state in which a defect occurs in the first gate driver on array sub-circuit. The present invention improves the yield rate of the gate driver on array circuit.

Abstract: A shift register is disclosed including an input module, an output module, a first reset module, a first pull-down module and a second pull-down module. The first pull-down module is configured to supply a reference signal to a first node and an output terminal in response to an active level of a first control signal. The second pull-down module is configured to supply the reference signal to the first node and the output terminal in response to an active level of a second control signal. The active levels of the first control signal and the second control signal occur alternately. Also disclosed are a gate driver circuit and a display apparatus.