Patents by Inventor Zhihong CHENG
Zhihong CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180138903Abstract: A CMOS buffer circuit includes a first branch circuit having first and second transistors connected in parallel between a voltage source and ground, and a second branch having third and fourth transistors connected in parallel between the voltage source and ground. The gates of the first and second transistors receive an input signal. The gates of the third and fourth transistors are connected to a first node between the drains of the first and second transistors. An output signal is provided at a second node between the drains of the third and fourth transistors. The first and fourth transistors have conductive channels of a first type, and the second and third transistors have conductive channels of a second type that is different from the first type. In one embodiment, the first and fourth transistors are high threshold voltage transistors and the second and third transistors are low threshold voltage transistors.Type: ApplicationFiled: August 16, 2017Publication date: May 17, 2018Inventor: Zhihong Cheng
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Patent number: 9946597Abstract: Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.Type: GrantFiled: September 4, 2016Date of Patent: April 17, 2018Assignee: NXP USA, INC.Inventors: Zhihong Cheng, Yin Guo
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Patent number: 9893771Abstract: A frequency shift keying (FSK) demodulation component having of a sampler that receives an FSK modulated signal, samples the received FSK modulated signal, and outputs the sampled signal. The FSK demodulation component further includes a low pass filter that filters the sampled signal, and a frequency shift detector that detects shifts in frequency of the low pass filtered sampled signal. The FSK demodulation component then outputs an indication of the detection of shifts in frequency of the low pass filtered sampled signal.Type: GrantFiled: August 11, 2016Date of Patent: February 13, 2018Assignee: NXP USA, INC.Inventors: Zhiling Sui, Zhijun Chen, Zhihong Cheng, SHixiang Nie
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Patent number: 9755623Abstract: A multi-bit flip-flop has first and second one-bit flip-flops. The multi-bit flip-flop employs inter-cell clock switch (CSW) sharing in which the first and second one-bit flip-flops share at least one clock switch. The multi-bit flip-flop may also employ intra-cell CSW sharing in which at least one of the first and second one-bit flip-flops shares at least one clock switch. The inter-cell CSW sharing enables implementation of multi-bit flip-flops with fewer clock switches and possibly fewer data devices, while reducing power consumption, including state retention power gating power reduction.Type: GrantFiled: August 7, 2016Date of Patent: September 5, 2017Assignee: NXP USA, INC.Inventors: Zhihong Cheng, Peidong Wang, Yang Wang
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Patent number: 9660849Abstract: A method of demodulating an FSK modulated input signal whose frequency varies between first and second frequencies. The input signal is delayed by a plurality of cycles, providing a second signal. A succession of phase reference signals having respective incrementally greater phase delays relative to the input signal are provided. Samples of the phase reference signals are taken at intervals determined by the second signal. A transition between the first and second frequencies is detected when the relative values of the samples of the phase reference signals remain constant during a plurality of intervals after varying. A high speed clock is not required to perform the demodulation.Type: GrantFiled: September 28, 2015Date of Patent: May 23, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Zhiling Sui, Zhijun Chen, Zhihong Cheng, Jiangtao Pan
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Publication number: 20170139772Abstract: Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.Type: ApplicationFiled: September 4, 2016Publication date: May 18, 2017Inventors: Zhihong Cheng, Yin Guo
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Publication number: 20170116365Abstract: An integrated circuit (IC) has a block of instances of cells aligned in rows of at least first and second heights. The instances of cells are selected from at least two different libraries of standard cells that have heights that are integer multiples of the first and second heights respectively as a function of performance criteria of the instances of cells. The floorplan provides respective numbers of rows of the different heights as a function of the ratios of the total widths of rows of the different heights needed to place the selected standard cells.Type: ApplicationFiled: September 4, 2016Publication date: April 27, 2017Inventors: ZHIHONG CHENG, Yifeng Liu, Peidong Wang
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Publication number: 20170070265Abstract: A frequency shift keying (FSK) demodulation component having of a sampler that receives an FSK modulated signal, samples the received FSK modulated signal, and outputs the sampled signal. The FSK demodulation component further includes a low pass filter that filters the sampled signal, and a frequency shift detector that detects shifts in frequency of the low pass filtered sampled signal. The FSK demodulation component then outputs an indication of the detection of shifts in frequency of the low pass filtered sampled signal.Type: ApplicationFiled: August 11, 2016Publication date: March 9, 2017Inventors: ZHILING SUI, Zhijun CHEN, Zhihong CHENG, Shixiang NIE
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Publication number: 20170063350Abstract: A multi-bit flip-flop has first and second one-bit flip-flops. The multi-bit flip-flop employs inter-cell clock switch (CSW) sharing in which the first and second one-bit flip-flops share at least one clock switch. The multi-bit flip-flop may also employ intra-cell CSW sharing in which at least one of the first and second one-bit flip-flops shares at least one clock switch. The inter-cell CSW sharing enables implementation of multi-bit flip-flops with fewer clock switches and possibly fewer data devices, while reducing power consumption, including state retention power gating power reduction.Type: ApplicationFiled: August 7, 2016Publication date: March 2, 2017Inventors: ZHIHONG CHENG, PEIDONG WANG, YANG WANG
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Patent number: 9490789Abstract: A clock switching circuit includes first and second clock lines, first and second selection lines, and first through fourth Muller C-elements. The Muller C-elements are connected to the clock and selection lines and first and second logic gates. First and second delay cells are connected to the clock lines and the second and fourth Muller C-elements. A first AND gate is connected to the first clock line, the first Muller C-element, and the first delay cell. A second AND gate is connected to the second delay cell, the third Muller C-element, and the second clock line, and an OR gate is connected to the first and second AND gates.Type: GrantFiled: April 27, 2016Date of Patent: November 8, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chaoxuan Tian, Zhihong Cheng, Zhiling Sui
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Publication number: 20160285658Abstract: A method of demodulating an FSK modulated input signal whose frequency varies between first and second frequencies. The input signal is delayed by a plurality of cycles, providing a second signal. A succession of phase reference signals having respective incrementally greater phase delays relative to the input signal are provided. Samples of the phase reference signals are taken at intervals determined by the second signal. A transition between the first and second frequencies is detected when the relative values of the samples of the phase reference signals remain constant during a plurality of intervals after varying. A high speed clock is not required to perform the demodulation.Type: ApplicationFiled: September 28, 2015Publication date: September 29, 2016Inventors: Zhiling Sui, Zhijun Chen, Zhihong Cheng, Jiangtao Pan
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Patent number: 9191021Abstract: A pipelined analog-to-digital converter (ADC) that converts an analog input voltage signal Vin into a digital output value Dout. The ADC has a sequence of stages including a first calibrated stage having: (1) an ADC sub-module that receives Vin and provides an ADC sub-module digital output value based on Vin, (2) a DAC sub-module that receives the ADC sub-module digital output value and outputs a corresponding analog voltage signal VDAC, (3) a first difference module that generates an analog residual-voltage signal based on a difference between Vin and VDAC, and (4) an artificial-noise-insertion module that inserts an analog artificial-noise voltage signal into the residual voltage signal to generate an analog combined voltage signal. The analog combined voltage signal is used to calibrate the first calibrated stage. The artificial-noise-insertion module generates the polarity of the artificial-noise voltage signal based on the polarity of the corresponding residual voltage signal.Type: GrantFiled: April 26, 2015Date of Patent: November 17, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Zhiling Sui, Zhijun Chen, Zhihong Cheng, Yanping Zhang
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Patent number: 9166585Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.Type: GrantFiled: August 20, 2014Date of Patent: October 20, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Amit Roy, Zhihong Cheng, Amit Kumar Dey, Vijay Tayal, Chetan Verma
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Patent number: 9148149Abstract: A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.Type: GrantFiled: February 7, 2014Date of Patent: September 29, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Zhihong Cheng, Peidong Wang
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Publication number: 20150102839Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.Type: ApplicationFiled: August 20, 2014Publication date: April 16, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Amit Roy, Zhihong Cheng, Amit Kumar Dey, Vijay Tayal, Chetan Verma
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Publication number: 20150091626Abstract: A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.Type: ApplicationFiled: May 15, 2014Publication date: April 2, 2015Inventors: Miaolin Tan, Zhihong Cheng, Juan Fu, Peidong Wang, Yali Wang
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Publication number: 20150084680Abstract: A state retention power gated (SRPG) cell includes a retention circuit coupled to a power gated circuit. The retention circuit stores state information of the power gated circuit before a low power period is started. A gated power supply coupled to the power gated circuit and to a first end of a power supply switch supplies a gated supply voltage to the power gated circuit during a non-low power period. A local power supply coupled to the retention circuit and to a second end of the power supply switch is coupled to the gated power supply in the non-low power period, and a non-gated power supply is coupled to the local power supply via an isolation element to isolate the non-gated power supply from the local power supply during the non-low power period, and to couple the non-gated power supply to the local power supply during the low power period.Type: ApplicationFiled: February 26, 2014Publication date: March 26, 2015Inventors: Zhihong Cheng, Zhijun Chen, Huabin Du, Peidong Wang, Shayan Zhang
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Patent number: 8987786Abstract: A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.Type: GrantFiled: May 15, 2014Date of Patent: March 24, 2015Assignee: Freescale Semiconductor, IncInventors: Miaolin Tan, Zhihong Cheng, Juan Fu, Peidong Wang, Yali Wang
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Patent number: 8941429Abstract: In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.Type: GrantFiled: August 6, 2013Date of Patent: January 27, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Zhihong Cheng
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Patent number: 8884669Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.Type: GrantFiled: August 12, 2013Date of Patent: November 11, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Xiaoxiang Geng, Zhihong Cheng, Huabin Du, Miaolin Tan