Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.

Abstract: Terahertz external modulator based on high electron mobility transistors belongs to the field of electromagnetic functional devices technology. This invention includes the semiconductor substrate (1), the epitaxial layer (2), and the modulation-unit array (4). The epitaxial layer (2) is set on the semiconductor substrate (1). The modulation-unit (4), the positive electrode (3), and the negative electrode (5) are all set on the epitaxial layer (2). The modulation-unit array includes at least three units with each of them is composed of high electron mobility transistors and metamaterial-structure. The gates of transistors connect to the negative electrode (5), and the sources and drains connect to the positive electrode (3). This invention is used for manipulation of spatial transmission terahertz waves. It could be operated at room temperatures, normal pressures, and non-vacuum condition. It does not need to load on the waveguide, thus is easy to package and use.

Abstract: Terahertz external modulator based on high election mobility transistors belongs to the field of electromagnetic functional devices technology. This invention includes the semiconductor substrate (1), the epitaxial layer (2), and the modulation-unit array (4). The epitaxial layer (2) is set on the semiconductor substrate (1). The modulation-unit (4), the positive electrode (3), and the negative electrode (5) are all set on the epitaxial layer (2). The modulation-unit array includes at least three units with each of them is composed of high electron mobility transistors and metamaterial-structure. The gates of transistors connect to the negative electrode (5), and the sources and drains connect to the positive electrode (3). This invention is used for manipulation of spatial transmission terahertz waves. It could be operated at room temperatures, normal pressures, and non-vacuum condition. It does not need to load on the waveguide, thus is easy to package and use.

Abstract: A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene material (4), a metal film (5), and photoresist patterns (6) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, wherein the source electrode 7 and drain electrode 9 are connected with a metal of the active region, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor.

Abstract: A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene material (4), a metal film (5), and photoresist patterns (6) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, wherein the source electrode 7 and drain electrode 9 are connected with a metal of the active region, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor.