Abstract: An enhanced HFET, comprising a HFET device body.

Abstract: The disclosure provides a method for preparing a self-aligned surface channel field effect transistor, and provides a power device. The method includes the following steps: depositing a first metal mask layer; preparing a first photoresist layer; forming a source area pattern and a drain area pattern; depositing a source metal layer and a drain metal layer on the source area pattern and the drain area pattern; peeling off and removing the first photoresist layer; depositing a second metal mask layer; preparing a second photoresist layer, and forming at least one gate area pattern closer toward the source metal layer by performing exposure and development; removing the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer by a wet corrosion; depositing a gate metal layer on the gate area pattern; and peeling off and removing the second photoresist layer.

Abstract: The present application discloses a semiconductor device and a method for forming a p-type conductive channel in a diamond using an abrupt heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method includes: forming a diamond layer on a substrate; forming one or multiple layers of a heterogeneous elementary substance or compound having an acceptor characteristic on an upper surface of the diamond layer; forming a heterojunction at an interface between the diamond layer and an acceptor layer; forming two-dimensional hole gas at one side of the diamond layer with a distance of 10 nm-20 nm away from the heterojunction; and using the two-dimensional hole gas as a p-type conductive channel. The method enables a concentration and a mobility of carriers to maintain stable at a temperature range of 0° C.-1000° C., thereby realizing normal operation of the diamond device at high temperature environment.

Abstract: The present disclosure relates to semiconductor devices, and in particular, to an enhancement-mode field effect transistor. This enhancement-mode field effect transistor includes a substrate, a channel layer formed on an upper surface of the substrate, a source electrode and a drain electrode respectively formed on both sides of the channel layer, and a gate electrode formed on an upper surface of the channel layer, a region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region. Carriers are absent in the carrier-free region, and carriers are present in the remaining portion of the channel layer.

Abstract: The present application discloses an unbalanced terahertz frequency doubler circuit with power handling capacity including a RF input waveguide, a quartz substrate and a RF output waveguide, where one end of the quartz substrate is disposed in a waveguide groove of the RF input waveguide and the other end of the quartz substrate is disposed in a waveguide groove of the RF output waveguide, where an input transition microstrip is disposed on the quartz substrate, and one end of the transition microstrip is connected to an output transition microstrip sequentially through a first transmission microstrip, a low pass filter, a RF matching microstrip and a second transmission microstrip, where anodes of four GaAs-based terahertz frequency multiplier diode groups are connected to the RF matching microstrip, and a cathode at the outermost position of each of the GaAs-based terahertz frequency multiplier diode groups is connected to a grounding quartz strip.

Abstract: A high-electron mobility transistor (HEMT) array terahertz wave modulator loaded in a waveguide is provided, which belongs to the technical field of electromagnetic functional devices and focuses on fast dynamic functional devices in the terahertz band. The device comprises a waveguide cavity and a modulation chip. The modulation chip comprises a semiconductor material substrate, a heterostructure material epitaxial layer, an artificial microstructure, and a socket circuit. The applied voltage controls the distribution change of the two-dimensional electron gas in the HEMT, which in turn controls the resonance mode conversion in the artificial microstructure, thereby control the transmission of electromagnetic waves in the waveguide. The modulator has a modulation depth of up to 96% and a modulation rate above 2 GHz. The invention can be realized by using micro-processing technology, and the preparation process is mature and reliable.

Abstract: A wideband terahertz modulator based on gradual openings, which belongs to the technical field of electromagnetic functional devices, includes: a semiconductor substrate; an epitaxial layer provided on the semiconductor substrate; a modulation units array, a positive voltage loading electrode and a negative voltage loading electrode which are provided on the epitaxial layer; wherein each modulation unit in the modulation units array comprises a disconnected H-shaped structure, a metal electrode located below an end of the opening of the disconnected H-shaped structure, and a semiconductor doped heterostructure located below the opening of the disconnected H-shaped structure; wherein in the disconnected H-shaped structures, adjacent modulation units have different opening positions; in a same row, the opening positions are linearly distributed and have a certain slope, and inclination slopes of the opening positions of two adjacent rows are opposite.

Abstract: An enhanced HFET, comprising a HFET device body.

Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.

Abstract: The present application discloses a semiconductor device and a method for forming an n-type conductive channel in a diamond using a heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method comprises: forming a diamond layer on a substrate; and depositing a ternary compound having a donor characteristic and graded components on an upper surface of the diamond layer to form a first donor layer, forming a graded heterojunction at an interface between the diamond layer and the first donor layer, forming two-dimensional electron gas at one side of the diamond layer adjacent to the graded heterojunction, and using the two-dimensional electron gas as the n-type conductive channel. The method enables a concentration and a mobility of carriers in the n-type diamond channel to reach 1013 cm?2 and 2000 cm2/V·s respectively.

Abstract: The present application discloses a semiconductor device and a method for forming an n-type conductive channel in a diamond using a heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method comprises: forming a diamond layer on a substrate; and depositing a ternary compound having a donor characteristic and graded components on an upper surface of the diamond layer to form a first donor layer, forming a graded heterojunction at an interface between the diamond layer and the first donor layer, forming two-dimensional electron gas at one side of the diamond layer adjacent to the graded heterojunction, and using the two-dimensional electron gas as the n-type conductive channel. The method enables a concentration and a mobility of carriers in the n-type diamond channel to reach 1013 cm?2 and 2000 cm2/V·s respectively.

Abstract: The present application discloses a semiconductor device and a method for forming a p-type conductive channel in a diamond using an abrupt heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method includes: forming a diamond layer on a substrate; forming one or multiple layers of a heterogeneous elementary substance or compound having an acceptor characteristic on an upper surface of the diamond layer; forming a heterojunction at an interface between the diamond layer and an acceptor layer; forming two-dimensional hole gas at one side of the diamond layer with a distance of 10 nm-20 nm away from the heterojunction; and using the two-dimensional hole gas as a p-type conductive channel. The method enables a concentration and a mobility of carriers to maintain stable at a temperature range of 0° C.-1000° C., thereby realizing normal operation of the diamond device at high temperature environment.

Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.

Abstract: Terahertz external modulator based on high electron mobility transistors belongs to the field of electromagnetic functional devices technology. This invention includes the semiconductor substrate (1), the epitaxial layer (2), and the modulation-unit array (4). The epitaxial layer (2) is set on the semiconductor substrate (1). The modulation-unit (4), the positive electrode (3), and the negative electrode (5) are all set on the epitaxial layer (2). The modulation-unit array includes at least three units with each of them is composed of high electron mobility transistors and metamaterial-structure. The gates of transistors connect to the negative electrode (5), and the sources and drains connect to the positive electrode (3). This invention is used for manipulation of spatial transmission terahertz waves. It could be operated at room temperatures, normal pressures, and non-vacuum condition. It does not need to load on the waveguide, thus is easy to package and use.

Abstract: Terahertz external modulator based on high election mobility transistors belongs to the field of electromagnetic functional devices technology. This invention includes the semiconductor substrate (1), the epitaxial layer (2), and the modulation-unit array (4). The epitaxial layer (2) is set on the semiconductor substrate (1). The modulation-unit (4), the positive electrode (3), and the negative electrode (5) are all set on the epitaxial layer (2). The modulation-unit array includes at least three units with each of them is composed of high electron mobility transistors and metamaterial-structure. The gates of transistors connect to the negative electrode (5), and the sources and drains connect to the positive electrode (3). This invention is used for manipulation of spatial transmission terahertz waves. It could be operated at room temperatures, normal pressures, and non-vacuum condition. It does not need to load on the waveguide, thus is easy to package and use.

Abstract: A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene material (4), a metal film (5), and photoresist patterns (6) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, wherein the source electrode 7 and drain electrode 9 are connected with a metal of the active region, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor.

Abstract: A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene material (4), a metal film (5), and photoresist patterns (6) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, wherein the source electrode 7 and drain electrode 9 are connected with a metal of the active region, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor.