Patents by Inventor Zhihong Wang

Zhihong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10589397
    Abstract: A difference between a first expected required polish time for a first substrate and a second expected required polish time for a second substrate is determined using a first pre-polish thickness and a second pre-polish thickness measured at an in-line metrology station. A duration of an initial period is determined based on the difference between the first expected required polish time and the second expected required polish time. For the initial period at a beginning of a polishing operation, no pressure is applied to whichever of the first substrate and the second substrate has a lesser expected required polish time while simultaneously pressure is applied to whichever of the first substrate and the second substrate has a greater expected required polish time. After the initial period, pressure is applied to both the first substrate and the second substrate.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: March 17, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Alain Duboust, Wen-Chiang Tu, Shih-Haur Shen, Jimin Zhang, Ingemar Carlsson, Boguslaw A. Swedek, Zhihong Wang, Stephen Jew, David H. Mai, Huyen Tran
  • Patent number: 10464184
    Abstract: Before a first surface of a substrate is polished using a chemical mechanical process, the substrate is transferred to a modification station. The substrate comprises a side wall connected with the first surface at an edge and a second surface opposite to the first surface and also connected to the side wall. The first surface is substantially flat. The side wall is substantially perpendicular to the first surface. The edge of the substrate is modified at the modification station by removing material from a region of the first surface. The side wall of the substrate is a boundary of the region. The modified edge comprises a modified first surface that tapers within the region towards the second surface. The side wall remains substantially perpendicular to the first surface.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: November 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Jimin Zhang, Zhihong Wang, Wen-Chiang Tu
  • Patent number: 10307987
    Abstract: Embodiments of the present disclosure provide for materials that include conch shell structures, methods of making conch shell slices, devices for storing energy, and the like.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: June 4, 2019
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Xixiang Zhang, Yingbang Yao, Zhihong Wang
  • Patent number: 10261905
    Abstract: A method for accessing a cache including reading an access instruction for acquiring data; determining, according to a delay identifier carried by the access instruction, whether the access instruction produces a delay; accessing the cache and performing, according to a location identifier carried by the access instruction, a pre-fetch operation if a delay is produced; and modifying, according to a location where the data required by the access instruction is acquired, the delay identifier and the location identifier carried by the access instruction. The technical solutions solve the problem of a low hit rate upon cache access, reduce the probability of misses, and reduce an access delay caused by a level-by-level access to each level of cache upon target data acquisition, which correspondingly lowers the power consumption generated upon the cache access and improves the CPU performance.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 16, 2019
    Assignee: Alibaba Group Holding Limited
    Inventors: Ling Ma, Zhihong Wang, Lei Zhang
  • Patent number: 10199281
    Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: February 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
  • Publication number: 20190035699
    Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
    Type: Application
    Filed: October 2, 2018
    Publication date: January 31, 2019
    Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
  • Patent number: 10129387
    Abstract: Embodiments of the present disclosure disclose a terminal anti-lost method and a terminal, to resolve a problem that a lost terminal is difficult to find when a user discovers in a timely manner that the terminal is lost. The method in the embodiments of the present disclosure includes: first detecting, by the terminal when receiving a specific instruction, whether the terminal is currently in a lock screen state, where the specific instruction represents an instruction of controlling the terminal to decrease volume and/or an instruction of preventing the terminal from receiving a carrier signal; and skipping executing, by the terminal, the instruction when it is determined that the terminal is in the lock screen state, and controlling the terminal to increase the volume and/or play an alarm tone by using a loudspeaker.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: November 13, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhihong Wang, Mingxing Cai
  • Patent number: 10103073
    Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 16, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
  • Patent number: 10094842
    Abstract: An automatic biochemical analyzer, comprises a reaction wheel comprising an inner ring and an outer ring, wherein the reaction wheel is equally divided into multiple cuvette positions; the inner ring and the outer ring have a photoelectric detection position, a sample injecting position, a reagent injecting position, a sample stirring position, a reagent stirring position and a cuvette cleaning position; the photoelectric detection position of the inner ring is offset relative to that of the outer ring by a first cuvette position along a counterclockwise or clockwise direction; and the sample injecting positions, the reagent injecting positions, the sample stirring positions, and the reagent stirring positions of the inner ring are offset relative to those of the outer ring by a second cuvette position along the same direction, the first cuvette position is equal to the second cuvette position, or a difference between those two is one cuvette position.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: October 9, 2018
    Assignee: Shenzhen Mindray Bio-Medical Electronics Co., Ltd.
    Inventors: Zhihong Wang, Qisong Liu
  • Publication number: 20180166347
    Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
    Type: Application
    Filed: February 7, 2018
    Publication date: June 14, 2018
    Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
  • Patent number: 9966961
    Abstract: A system on chip (SoC) is connected to multiple off-chip devices, where the off-chip devices share IO pads of the SoC. A pin-mux circuit is used to facilitate the IO pad sharing. The pin-mux circuit can be addressed using just one control register and a decoder, which allows the IO pads to be easily and flexibly assigned. The decoder generates pin-mux control bits based on a configuration word stored in the control register. The pin-mux circuit assigns IO pads of the SoC to the off-chip devices. Device controllers of the SoC provide output bits to corresponding ones of the devices by way of the IO pads, and the devices provide input bits to the device controllers via the IO pads. Chip area is saved by using a register-decoder scheme, and set-up requires writing just the one control register.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 8, 2018
    Assignee: NXP USA, INC.
    Inventors: Yedong He, Zhihong Wang
  • Publication number: 20180113143
    Abstract: A sample analyzer, comprising a sample storage region, a sample-drawing channel, and a transport mechanism; the sample storage region being provided with a plurality of storage channels; the sample-drawing channel is provided with a sample-drawing position; the transport mechanism comprises an engagement slot, an actuation mechanism and a first moving mechanism; the engagement slot and the actuation mechanism are fixed on the first moving mechanism, the actuation mechanism comprises an actuator and a second moving mechanism, the actuator is drivable by at least one of the first moving mechanism and the second moving mechanism to realize the movement of the sample holder between the storage channels and the engagement slot; during sample drawing, the first moving mechanism drives the engagement slot to move to the sample-drawing channel, the actuation mechanism enables samples to pass through the sample-drawing position and to make a stop for sample drawing.
    Type: Application
    Filed: December 21, 2017
    Publication date: April 26, 2018
    Inventors: Zhihong WANG, Fating SHE, Peng ZHOU
  • Patent number: 9948722
    Abstract: Disclosed are a path computation element communication protocol (PCEP) session establishment method and device. The technical solution comprises: at a PCC or PCE node device side, before needing to establish a PCEP session, allocating a TCP connection communication end attribute to a PCC or a PCE at either end in the manner of static configuration/dynamic designation or election mechanism automatic allocation; or detecting whether to establish a TCP connection relationship, if not, actively connecting the opposite end, and if a plurality of TCP connection relationships has been established, simultaneously cutting off a plurality of connections at both ends, and reinitiating a TCP connection after waiting a random time respectively. The present invention achieves the establishment of a PCEP session in the multi-PCE cooperation computation scenario under the condition of meeting two constraint conditions which are specified by a protocol.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: April 17, 2018
    Assignee: ZTE CORPORATION
    Inventors: Xuping Cao, Zhihong Wang, Gang Lu, Jia Qian
  • Patent number: 9944506
    Abstract: A forklift truck with a forward-tilting cab and a method for reducing the container-loading height of the forklift truck, include a cab and a frame, the cab being connected to the frame so as to be able to tilt forward; and also including a locating mechanism, which is removably provided between the cab and frame when the cab is tilted forward to reduce the cab height, so as to locate the cab when the cab is tilted forward to a preset angle. When loading into a container, the cab of the forklift truck is tilted forward to a preset angle, so that the overall height of the forklift truck is reduced to a height suitable for loading in a container, and the locating mechanism is used to locate the cab, so that the cab is kept in a state in which it is tilted forward to a preset angle.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: April 17, 2018
    Assignee: Linde Material Handling GmbH
    Inventors: Marcus Taylor, Wayne Edmunds, Fenghua Shi, Clayton Greenman, Haihui Lian, Qingrong Xu, Zhihong Wang
  • Patent number: 9911664
    Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
  • Publication number: 20180056476
    Abstract: An apparatus for chemical mechanical polishing includes a platen having a surface to support a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad, a pad conditioner including a conductive body to be pressed against the polishing surface, an in-situ polishing pad thickness monitoring system including a sensor disposed in the platen to generate a magnetic field that passes through the polishing pad, and a controller configured to receive a signal from the monitoring system and generate a measure of polishing pad thickness based on a portion of the signal corresponding to a time that the sensor is below the conductive body of the pad conditioner.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 1, 2018
    Inventors: Jimin Zhang, Zhihong Wang, Harry Q. Lee, Brian J. Brown, Wen-Chiang Tu, William H. McClintock, Wei Lu
  • Publication number: 20170365532
    Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
    Type: Application
    Filed: September 1, 2017
    Publication date: December 21, 2017
    Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
  • Patent number: 9843497
    Abstract: A method and device for long-term storage of cross-domain path information are provided. The method is applied on a stateless PCE.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: December 12, 2017
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO. LTD.
    Inventors: Wenxiang Lv, Jiayu Wang, Gang Lu, Zhihong Wang, Xuping Cao
  • Patent number: 9836400
    Abstract: In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Kebing Wang, Zhaojuan Bian, Wei Zhou, Zhihong Wang
  • Publication number: 20170346939
    Abstract: Embodiments of the present disclosure disclose a terminal anti-lost method and a terminal, to resolve a problem that a lost terminal is difficult to find when a user discovers in a timely manner that the terminal is lost. The method in the embodiments of the present disclosure includes: first detecting, by the terminal when receiving a specific instruction, whether the terminal is currently in a lock screen state, where the specific instruction represents an instruction of controlling the terminal to decrease volume and/or an instruction of preventing the terminal from receiving a carrier signal; and skipping executing, by the terminal, the instruction when it is determined that the terminal is in the lock screen state, and controlling the terminal to increase the volume and/or play an alarm tone by using a loudspeaker.
    Type: Application
    Filed: December 30, 2014
    Publication date: November 30, 2017
    Inventors: Zhihong WANG, Mingxing CAI