Patents by Inventor Zhihong You
Zhihong You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7554309Abstract: Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.Type: GrantFiled: May 18, 2005Date of Patent: June 30, 2009Assignee: Texas Instruments IncorporatedInventors: John H. Carpenter, Jr., Brett J. Thompsen, Benjamin L. Amey, Zhihong You, Joseph A. Devore
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Publication number: 20090160493Abstract: A circuit for, and method of, generating a spread-spectrum clock signal. In one embodiment, the circuit includes: (a) a modulator configured to generate a modulated control value, and (b) a frequency synthesizer coupled to the modulator and configured to generate a spread-spectrum clock signal based on a variation of the modulated control value, the frequency synthesizer having a directly-derivable frequency response output.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: Texas Instruments IncorporatedInventors: Zhihong You, Liming Xiu
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Patent number: 7372340Abstract: A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a sequence differential stages o produce equally spaced clock phases. The frequency synthesis circuit includes a sequence of adder-and-register units that select one of the VCO clock phases. An output multiplexer receives each of the selected clock phases, and selects among these clock phases in sequence; the output of the multiplexer is applied to a first toggle flip-flop that changes state in response to rising edge transitions at the output of the multiplexer. A second toggle flip-flop is clocked by the output of the first toggle flip-flop, itself toggling in response to rising edge transitions at the output of the first toggle flip-flop. One or more additional flip-flops can be similarly connected in sequence.Type: GrantFiled: October 14, 2005Date of Patent: May 13, 2008Assignee: Texas Instruments IncorporatedInventors: Liming Xiu, Zhihong You
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Publication number: 20060261793Abstract: Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.Type: ApplicationFiled: May 18, 2005Publication date: November 23, 2006Applicant: Texas Instruments IncorporatedInventors: John Carpenter, Brett Thompsen, Benjamin Amey, Zhihong You, Joseph Devore
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Publication number: 20060145772Abstract: A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a sequence differential stages o produce equally spaced clock phases. The frequency synthesis circuit includes a sequence of adder-and-register units that select one of the VCO clock phases. An output multiplexer receives each of the selected clock phases, and selects among these clock phases in sequence; the output of the multiplexer is applied to a first toggle flip-flop that changes state in response to rising edge transitions at the output of the multiplexer. A second toggle flip-flop is clocked by the output of the first toggle flip-flop, itself toggling in response to rising edge transitions at the output of the first toggle flip-flop. One or more additional flip-flops can be similarly connected in sequence.Type: ApplicationFiled: October 14, 2005Publication date: July 6, 2006Applicant: Texas Instruments IncorporatedInventors: Liming Xiu, Zhihong You
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Patent number: 7065172Abstract: An electronic system (10) includes a phase-locked loop (30) and a frequency synthesis circuit (20), for generating a jitter-free output clock (CLK1, CLK2) at a desired frequency. The phase-locked loop (30) includes a voltage-controlled oscillator (37) that produces a number (N) of equally spaced clock phases at a frequency (fVCO) that depends also upon a programmable feedback frequency divider (38) and a prescale divider (32). The frequency synthesis circuit (20) generates the output clock (CLK1, CLK2) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A central processing unit (12), either itself or from a look-up table (13), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (f), by way of a minimization of the frequency error.Type: GrantFiled: February 26, 2003Date of Patent: June 20, 2006Assignee: Texas Instruments IncorporatedInventors: Liming Xiu, Zhihong You
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Patent number: 6940937Abstract: A clock synthesis circuit (22) including a phase-locked loop (25) and one or more frequency synthesis circuits (27; 77; 227; 237) is disclosed. A disclosed implementation of the phase-locked loop (25) includes a voltage-controlled oscillator (30) having an even number of differential stages (31) to produce an even number of equally spaced clock phases. In one arrangement, the frequency synthesis circuit (27) includes two adder legs that generate select signals applied to first and second multiplexers (40a, 40b), for selecting among the clock phases from the voltage-controlled oscillator (30). The outputs of the first and second multiplexers (40a, 40b) are applied to a two-to-one multiplexer (46) which is controlled by the output clock signal (CLK1), to drive clock edges to a T flip-flop (48) to produce the output clock signals (CLK1, CLK2).Type: GrantFiled: December 24, 2001Date of Patent: September 6, 2005Assignee: Texas Instruments IncorporatedInventors: Liming Xiu, Zhihong You
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Publication number: 20040008805Abstract: An electronic system (10) includes a phase-locked loop (30) and a frequency synthesis circuit (20), for generating a jitter-free output clock (CLK1, CLK2) at a desired frequency. The phase-locked loop (30) includes a voltage-controlled oscillator (37) that produces a number (N) of equally spaced clock phases at a frequency (fVCO) that depends also upon a programmable feedback frequency divider (38) and a prescale divider (32). The frequency synthesis circuit (20) generates the output clock (CLK1, CLK2) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A central processing unit (12), either itself or from a look-up table (13), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (ƒ), by way of a minimization of the frequency error.Type: ApplicationFiled: February 26, 2003Publication date: January 15, 2004Applicant: Texas Instruments IncorporatedInventors: Liming Xiu, Zhihong You
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Publication number: 20030118142Abstract: A clock synthesis circuit (22) including a phase-locked loop (25) and one or more frequency synthesis circuits (27; 77; 227; 237) is disclosed. A disclosed implementation of the phase-locked loop (25) includes a voltage-controlled oscillator (30) having an even number of differential stages (31) to produce an even number of equally spaced clock phases. In one arrangement, the frequency synthesis circuit (27) includes two adder legs that generate select signals applied to first and second multiplexers (40a, 40b), for selecting among the clock phases from the voltage-controlled oscillator (30). The outputs of the first and second multiplexers (40a, 40b) are applied to a two-to-one multiplexer (46) which is controlled by the output clock signal (CLK1), to drive clock edges to a T flip-flop (48) to produce the output clock signals (CLK1, CLK2).Type: ApplicationFiled: December 24, 2001Publication date: June 26, 2003Applicant: Texas Instruments IncorporatedInventors: Liming Xiu, Zhihong You