Abstract: The present invention provides a method for upgrading an application, and the method includes: obtaining a patch package corresponding to a current installation package of an application; removing a customized information portion from the current installation package and obtaining a data portion of the current installation package; generating a data portion of a new installation package according to the patch package and the data portion of the current installation package; obtaining the new installation package by adding the customized information portion to the data portion and the new installation package; installing the new installation package.

Abstract: A device receives information associated with a functional model, and generates the functional model based on the received information and with a technical computing environment (TCE), where the functional model including nodes, inputs, and outputs. The device also automatically detects architecture information from an architecture model associated with the functional model, and automatically assigns, based on the architecture information, at least one signal between two nodes of the functional model, a node and an input of the functional model, or a node and an output of the functional model. The device obtains information for code generation based on the assigned at least one signal, and stores the information for code generation.

Abstract: A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.

Abstract: The present invention provides a method for upgrading an application, and the method includes: obtaining a patch package corresponding to a current installation package of an application; removing a customized information portion from the current installation package and obtaining a data portion of the current installation package; generating a data portion of a new installation package according to the patch package and the data portion of the current installation package; obtaining the new installation package by adding the customized information portion to the data portion and the new installation package; installing the new installation package.

Abstract: The present invention provides a method, a device, and a system for delivering live content. A pre-delivery request with respect to live content is sent to a CDN cache device, and the CDN cache device caches the live content according to the pre-delivery request with respect to the live content before a user views the live content, thereby solving the problems of a long delay and poor user experience in playing live content that is not cached because a part of live content cannot be cached in the prior art, ensuring the play quality of all live content, and improving user experience.

Abstract: Methods, systems and computer program products are disclosed for automatically generating hardware description language code from a model. The hardware description language code may be generated from a graphical program/model, such as a block diagram model. The hardware description language code may also be generated from a text-based program/model, such as a model created using MATLAB® tools. In particular, the present invention provides for the automatic code generation of an interface between components in the model. The present invention may provide options for selecting at least one of multiple types or styles of the component interfaces in the model. The selection of the interface types or styles may be controlled by the user or inferred by other parameters, such as implementation parameters.

Abstract: A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.

Abstract: A system generates a state diagram model in a graphical modeling system, where the state diagram model includes at least one state. A condition statement is associated with the at least one state, and defines a condition upon which one or more actions associated with the at least one state are executed.

Abstract: The present invention provides a state diagramming environment in a computing device that enables the conversion of a state diagram into a hardware description language. To achieve this conversion, the present invention generates an intermediate representation of the state diagram. The intermediate representation is checked against a set of predefined restrictions for compliance. The state diagramming environment converts the intermediate representation of the state diagram into a hardware description language, such as VHDL or Verilog.

Abstract: Methods and systems for providing a synchronous model in a modeling environment are disclosed. The predetermined operations of the model, such as a transition to a state in a state-based modeling environment, are implicitly synchronized with a signal selected by users, such as a clock signal. The predetermined operations of the model may be synchronized on a rising and/or falling edge of the clock signal. The synchronization of the operations is guarded in which the predetermined operation of the model occurs only on the synchronization signal selected by the users while other operations may occur at any time when the model is activated.

Abstract: The present invention provides a user of a state diagramming environment with the ability to specify if the user wants to develop a Moore machine or a Mealy machine. To achieve this, a set of predefined requirements is provided that restricts the state diagram semantics to either semantics of a Moore or Mealy machine. When a user provides a state diagram that does not conform to the set of requirements, the state diagram is identified as non-conforming and the user is notified of the non-conformance. The user is given information describing what aspects of the state diagram do not conform, thereby, allowing the user to quickly identify any errors that have been made. As a result of the present invention, the burden placed on the user is reduced and the time spent debugging is minimized.

Abstract: A system generates a state diagram model in a graphical modeling system, where the state diagram model includes at least one state. A condition statement is associated with the at least one state, and defines a condition upon which one or more actions associated with the at least one state are executed.

Abstract: The present invention provides a state diagramming environment in a computing device that enables the conversion of a state diagram into a hardware description language. To achieve this conversion, the present invention generates an intermediate representation of the state diagram. The intermediate representation is checked against a set of predefined restrictions for compliance. The state diagramming environment converts the intermediate representation of the state diagram into a hardware description language, such as VHDL or Verilog.