Patents by Inventor Zhijian Mou

Zhijian Mou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4974186
    Abstract: The multiplier according to the invention comprises N shift registers (RD.sub.O, . . . , RD.sub.N-1) containing the words x.sub.i on B bits, N conditional adders (AdC.sub.O, . . . , AdC.sub.N-1) each adding to the partial sum which they receive a constant coefficient (a.sub.1), conditional on the value of the bit (x.sub.i,j) which they receive from the associated register (RD.sub.1) and an adder accumulator (AdAc). The digital filter using such a multiplier also comprises a parallel word input register.
    Type: Grant
    Filed: January 24, 1989
    Date of Patent: November 27, 1990
    Assignee: Etat Francais Represente par le Ministere des Postes, des Telecommunication et de L'Espace (CNET)
    Inventors: Pierre Duhamel, Zhijian Mou, Michel Cand