Patents by Inventor Zhijun NIU

Zhijun NIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11231610
    Abstract: The present disclosure is related to a display panel. The display panel may include a first light shielding layer (101) in a display region and a second light shielding layer (212) opposite the first light shielding layer (101) in the display region. The first light shielding layer (101) may include a plurality of first openings (112), and the second light shielding layer (212) may include a plurality of second openings (222). The display region may include a middle display region (20A) and a periphery display region (20B). An area of each of the plurality of the first openings (112) in the periphery display region (20B) may be smaller than an area of each of the plurality of the first openings (112) in the middle display region (20A).
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 25, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaokang Wang, Yanqing Chen, Jianyun Xie, Wei Li, Cheng Li, Le Sun, Wei Zhang, Xin Zhao, Zhijun Niu, Yezhou Fang, Pan Guo, Yanfeng Li, Weida Qin, Ning Wang
  • Publication number: 20210325719
    Abstract: The present disclosure is related to a display panel. The display panel may include a first light shielding layer (101) in a display region and a second light shielding layer (212) opposite the first light shielding layer (101) in the display region. The first light shielding layer (101) may include a plurality of first openings (112), and the second light shielding layer (212) may include a plurality of second openings (222). The display region may include a middle display region (20A) and a periphery display region (20B). An area of each of the plurality of the first openings (112) in the periphery display region (20B) may be smaller than an area of each of the plurality of the first openings (112) in the middle display region (20A).
    Type: Application
    Filed: July 19, 2018
    Publication date: October 21, 2021
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE Technology Group Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiaokang Wang, Yanqing Chen, Jianyun Xie, Wei Li, Cheng Li, Le Sun, Wei Zhang, Xin Zhao, Zhijun Niu, Yezhou Fang, Pan Guo, Yanfeng Li, Weida Qin, Ning Wang
  • Patent number: 10903249
    Abstract: An array substrate including a plurality of terminals, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer include an insulating layer therebetween, wherein a plurality of first electrode plates and a plurality of second electrode plates are formed in the first conductive layer and the second conductive layer, respectively, the first electrode plates and the second electrode plates are opposite to each other to constitute a capacitor structure, the terminals are provided in the same layer as the first conductive layer or the second conductive layer, or the terminals are provided in the same layer as a third conductive layer between the first conductive layer and the second conductive layer. A method of manufacturing an array substrate and a display device is provided.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: January 26, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Zhang, Hui Li, Tianlei Shi, Jonguk Kwak, Yezhou Fang, Wenlong Zhang, Xu Zhang, Zhijun Niu, Ruize Jiang, Yanwei Ren, Yu Liu
  • Publication number: 20200227446
    Abstract: An array substrate including a plurality of terminals, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer include an insulating layer therebetween, wherein a plurality of first electrode plates and a plurality of second electrode plates are formed in the first conductive layer and the second conductive layer, respectively, the first electrode plates and the second electrode plates are opposite to each other to constitute a capacitor structure, the terminals are provided in the same layer as the first conductive layer or the second conductive layer, or the terminals are provided in the same layer as a third conductive layer between the first conductive layer and the second conductive layer. A method of manufacturing an array substrate and a display device is provided.
    Type: Application
    Filed: March 29, 2018
    Publication date: July 16, 2020
    Inventors: Wei ZHANG, Hui LI, Tianlei SHI, Jonguk KWAK, Yezhou FANG, Wenlong ZHANG, Xu ZHANG, Zhijun NIU, Ruize JIANG, Yanwei REN, Yu LIU
  • Publication number: 20190172854
    Abstract: An array substrate including a plurality of terminals, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer include an insulating layer therebetween, wherein a plurality of first electrode plates and a plurality of second electrode plates are formed in the first conductive layer and the second conductive layer, respectively, the first electrode plates and the second electrode plates are opposite to each other to constitute a capacitor structure, the terminals are provided in the same layer as the first conductive layer or the second conductive layer, or the terminals are provided in the same layer as a third conductive layer between the first conductive layer and the second conductive layer. A method of manufacturing an array substrate and a display device is provided.
    Type: Application
    Filed: March 29, 2018
    Publication date: June 6, 2019
    Inventors: Wei ZHANG, Hui LI, Tianlei SHI, Jonguk KWAK, Yezhou FANG, Wenlong ZHANG, Xu ZHANG, Zhijun NIU, Ruize JIANG, Yanwei REN, Yu LIU