Abstract: A shift register and a display panel. The shift register includes an output adjustment module, a trigger write module, and a node adjustment module. A first terminal of the output adjustment module inputs a first clock signal. A second terminal of the output adjustment module inputs a first power signal. The output adjustment module is configured to adjust the shift register to output the first clock signal or the first power signal according to the signal on a first control node and the signal on a second control node of the output adjustment module. The trigger write module is configured to write a trigger signal to the second control node according to the clock signal of the control terminal of the trigger write module. The node adjustment module is configured to adjust the signal on the first control node.

Abstract: An array base plate, a display panel and a display apparatus. The array base plate includes a display area and a non-display area arranged adjacently. The array base plate includes: a substrate; a semiconductor layer located on the substrate and including a plurality of semiconductor portions distributed in an array along a first direction and a second direction; and one or more electrostatic protection portions each including a connection end and a free end opposing to each other, the connection end being connected with at least one of the semiconductor portions, and the free end extending from the connection end to the non-display area. In the present application, the electrostatic protection performance of the array base plate can be effectively improved by arranging the electrostatic protection portions.

Abstract: An array substrate and a display panel. The array substrate includes: a substrate; a patterned shielding layer, having a fixed potential, arranged on one side of the substrate, and includes multiple shielding units connected to each other; and a driving circuit layer, arranged on one side of the shielding layer away from the substrate and comprising multiple driving transistors. An orthographic projection of each of the plurality of driving transistors projected on the shielding layer at least partially covers a corresponding one of the shielding units.

Abstract: A shift register and a display panel. The shift register includes an output adjustment module, a trigger write module, and a node adjustment module. A first terminal of the output adjustment module inputs a first clock signal. A second terminal of the output adjustment module inputs a first power signal. The output adjustment module is configured to adjust the shift register to output the first clock signal or the first power signal according to the signal on a first control node and the signal on a second control node of the output adjustment module. The trigger write module is configured to write a trigger signal to the second control node according to the clock signal of the control terminal of the trigger write module. The node adjustment module is configured to adjust the signal on the first control node.

Abstract: A thin film transistor array substrate, a display panel and a display device. The thin film transistor array substrate includes a semiconductor layer, a gate layer and a source-drain layer arranged in a stacked manner, two insulating layers respectively located between the semiconductor layer and the gate layer and between the gate layer and the source-drain layer, the semiconductor layer comprises a source region, a drain region and a channel region located between the source region and the drain region, the channel region is doped with a p-type impurity, a molecular weight of the p-type impurity in the channel region is equal to or greater than 25, a range of a doping depth of the p-type impurity in the channel region is 1 nm to 20 nm.

Abstract: A display panel and a display device are provided. The display panel comprise a substrate having a display region, a plurality of pixel units arranged in an array and disposed in the display region of the substrate, a conductive member disposed in a peripheral region of the display region, a plurality of input pins electrically connected to the conductive member and transferring a voltage of an external power supply to the conductive member, and a plurality of power supply lines electrically connected to the conductive member and transferring the voltage from the conductive member to the pixel units.

Abstract: A display panel and a display device are provided. The display panel comprise a substrate having a display region, a plurality of pixel units arranged in an array and disposed in the display region of the substrate, a conductive member disposed in a peripheral region of the display region, a plurality of input pins electrically connected to the conductive member and transferring a voltage of an external power supply to the conductive member, and a plurality of power supply lines electrically connected to the conductive member and transferring the voltage from the conductive member to the pixel units.