Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the first semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor.

Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

Abstract: The present disclosure provides a memory device that includes a film stack having functional tiers stacked in a first direction. Each functional tier includes a first dielectric layer and a conductive layer. The memory device also includes channel structures disposed in an array core region, wherein each channel structure extends through the film stack in the first direction. Each channel structure includes a control gate in a center, a memory film that is disposed on a sidewall of the control gate and includes a ferroelectric film. Each channel structure also includes a channel layer disposed on a sidewall of the memory film.

Abstract: A touch control structure is provided. The touch control structure includes a plurality of first mesh electrodes respectively in a plurality of rows and a plurality of second mesh electrodes respectively in a plurality of columns. A respective one of the plurality of second mesh electrodes includes a plurality of second mesh blocks consecutively connected in a respective column. A respective one of the plurality of first mesh electrodes comprises a plurality of first mesh blocks and a plurality of third mesh blocks alternately arranged in a respective row. The respective second mesh block is in a space between a first adjacent third mesh block, a second adjacent third mesh block, a first adjacent first mesh block, a second adjacent first mesh block, a third adjacent first mesh block, and a fourth adjacent first mesh block.

Abstract: A four-notch flexible wearable ultra-wideband antenna fed by coplanar waveguide, includes a flexible base. A ground plane, a radiation patch and a feeder are arranged on the flexible base. There are several resonant tanks on the feeder and the radiation patch. The flexible base is made of insulating flexible material, and the feeder, the radiation patch and the ground plane are made of conductive flexible material. The four-notch flexible wearable ultra-wideband antenna fed by coplanar waveguide of the present application can be prepared by layer-by-layer assembly technology, spray printing or printed circuit board technology, and has the advantages of miniaturization and low profile, compact structure, convenient production, good conformality, wearable and other advantages.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.

Abstract: The present invention belongs to the field of medicinal chemistry, and relates to a novel KRAS G12C protein inhibitor, a preparation method and use thereof. In particular, the present invention provides a compound of formula I, which can be used as a high-efficiency KRAS G12C protein inhibitor and has various pharmacological activities against tumors, proliferative diseases, inflammation, autoimmune diseases, etc.

Abstract: The application discloses a mixed-spray firefighting device, which includes a water nozzle and a powder nozzle. The water nozzle is disposed around an outside of the powder nozzle, and a powder spray port of the powder nozzle is provided behind a water spray port of the water nozzle. A fire-extinguishing agent powder sprayed from the powder nozzle and a water flow sprayed from the water nozzle are mixed in air outside the firefighting device. The fire-extinguishing agent powder is preferably sodium polyacrylate resin powder. The application solves the technical bottleneck of using the sodium polyacrylate resin powder as a fire-extinguishing agent in the prior art, so that the sodium polyacrylate resin powder can be sprayed into a fire field smoothly and continuously without blocking the powder spray port.

Abstract: Disclosed is a mixed jet flow fire extinguishing system, including a water spray nozzle and a powder spray nozzle. A water spray port of the water spray nozzle and a powder spray port of the powder spray nozzle do not overlap; super absorbent resin powder sprayed from the powder spray nozzle is externally mixed in the air with a water flow sprayed from the water spray nozzle. A powder spray direction A of the powder spray nozzle is inclined relative to a water flow spray direction B of the water spray nozzle. The technical bottleneck of using sodium polyacrylate resin powder as a fire extinguishing agent in the prior art is solved, so that the sodium polyacrylate resin powder can be smoothly and continuously sprayed into a fire, without blocking the powder spray port.

Abstract: The present application provides a pharmaceutical composition of a prolyl hydroxylase inhibitor and a preparation method therefor. In particular, the present application provides a composition comprising a compound represented by formula (I) or a pharmacologically acceptable salt thereof and at least one water-soluble filler. The composition provided by the present application has a rapid dissolution rate and good stability.

Abstract: The present invention relates to a sodium polyacrylate super absorbent resin for blood absorption with a gradual hierarchical structure. When a blood simulant solution is used as the detection medium, according to ISO 19699-1:2017(E), the absorption capacity of the blood simulant solution is ?18.0 g/g, Preferably ?18.5 g/g; the absorption rate of the blood simulant solution is ?45 s, preferably ?40 s, more preferably ?38 s; when human blood is used as the detection medium, according to ISO 19699-1:2017(E), the absorption capacity of the human blood is ?8.0 g/g, preferably ?8.3 g/g, more preferably ?8.6 g/g; the absorption rate of the human blood is ?45 s, preferably ?40 s, more preferably ?35 s, most preferably ?25 s.

Abstract: A fluid valve includes a main valve body, a valve seat, a valve core and a valve actuator. The main valve body has a fluid inlet, and a fluid outlet. The valve core includes a core body having a main passage channel, a core inlet, and a core outlet. The core body has a curved guiding surface for forming a residual passage channel between the curved guiding surface and the valve seat. The valve core may be moved between a fully opened position, a partially opened position, and a fully closed position. In the partially opened position, the valve core is moved such that the fluid inlet is arranged to communicate with to the core inlet and the residual passage channel for allowing passage of fluid from the fluid inlet to the fluid outlet through the main passage channel and the residual passage channel.