Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, a first stop layer on the sacrificial layer, an N-type doped semiconductor layer on the first stop layer, and a dielectric stack on the N-type doped semiconductor layer are sequentially formed. A plurality of channel structures each extending vertically through the dielectric stack and the N-type doped semiconductor layer are formed, stopping at the first stop layer. The dielectric stack is replaced with a memory stack, such that each of the plurality of channel structures extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate, the sacrificial layer, and the first stop layer are sequentially removed to expose an end of each of the plurality of channel structures. A conductive layer is formed in contact with the ends of the plurality of channel structures.

Abstract: A semiconductor device includes a first stack of layers stacked on a substrate. The first stack of layers includes a source connection layer that is formed by replacing source sacrificial layers. The semiconductor device includes a channel structure that extends in the first stack of layers. The channel structure includes a channel layer that is in contact with the source connection layer in the first stack of layers. Further, the semiconductor device includes a shield structure formed in the first stack of layers. The shied structure encloses a stack of layers without the source connection layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region and word line pick-up structures in a first portion of a second region. The first region and the second region are arranged in a first direction. The 3D memory device also includes word lines each extending in the first region and a second portion of the second region. The first portion and the second portion of the second region are arranged in a second direction perpendicular to the first direction. The 3D memory device also includes dummy channel structures in the second portion of the second region. Adjacent channel structures are spaced apart from each other by a first distance. Adjacent dummy channel structures are spaced apart from each other by a second distance that is smaller than the first distance.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: A nucleic acid loading device, including a housing, a carrying module, a motion module, a liquid circuit module and a control module. The motion module includes a support platform, first and second driving mechanisms, and a carrying member. The liquid circuit module is configured to control a reagent to flow into and out of a reactor. The control module is connected with the motion module and the liquid circuit module, and the control module is configured to control the first and second driving mechanisms, the liquid circuit module and the temperature control unit. A first face of a semiconductor cooler heats or refrigerates during operation, providing heat for an accommodating seat through a heat conducting body such that the reactor can be at different ambient temperatures. The cooperation between the motion and liquid circuit modules may achieve automation and industrialization of loading a sample into the reactor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.

Abstract: A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: An optical system including a first light source, a first lens, and a light splitting module, wherein the light splitting module has a first splitter, a second lens, a first camera and a second camera, the first lens is configured for receiving a first light beam from the first light source and collimating the first light beam onto a sample, and for receiving and collimating a light beam from the sample, the second lens is configured for focusing the collimated light beam from the first lens to the first camera and the second camera, the first splitter is configured for splitting the focused light beam from the second lens into a second light beam and a third light beam, the first camera is configured for receiving the second light beam, and the second camera is configured for receiving the third light beam.

Abstract: A method and device for detecting bright spots on an image. The image is acquired from a field of view where a base extension reaction occurs, multiple nucleic acid molecules with optically detectable labels exist in the field of view where the base extension reaction occurs, and at least some of the nucleic acid molecules appear as bright spots on the image. The method includes preprocessing the image to obtain a preprocessed image; determining a critical value to simplify the preprocessed image to obtain a simplified image, determining a first bright spot detection threshold on the basis of the preprocessed image, and identifying candidate bright spots on the image on the basis of the preprocessed image and the simplified image, including determining a pixel matrix that satisfies at least two of conditions as a candidate bright spot.

Abstract: The present disclosure discloses a method and a system for imaging. The method for imaging objects using the system for imaging. The system for imaging comprises a lens. The objects comprise a first object, a second object and a third object located at different positions on a first preset track. The method for imaging comprises: allowing the lens and the first preset track to move relatively in a first predetermined relationship to acquire a clear image of the third object using the system for imaging without focusing, the first predetermined relationship is determined by a focal plane position of the first object and a focal plane position of the second object. The aforementioned method for imaging is high in imaging efficiency and is capable of fast focusing according to the first predetermined relationship even if focus tracking fails so that the blurring of a photographed image due to defocusing is avoided.

Abstract: A vibration damping structure (60), a detection system and a sequencing system. The vibration damping structure (60) is used in the detection system. The vibration damping structure (60) comprises a main body (62) and a support body (64), the main body (62) is connected to the detection system by means of the support body (64), the main body (62) comprises an imaging module (10), an upper layer structure (66), a lower layer structure (68) and an intermediate structure (70), the imaging module (10) is mounted on the upper layer structure (66), the lower layer structure (68) bears the upper layer structure (66) by means of the intermediate structure (70), and the natural frequency of the main body (62) is greater than or equal to ?{square root over (2)} times the internal excitation frequency.

Abstract: The disclosure discloses an alignment method, device, and system.

Abstract: The present disclosure discloses a method for controlling a base sequence determination, a base sequence determination system, and a control device. The base sequence determination system includes a fluid device and an optical device, a reaction device includes a first component and a second component, and a repeated executable unit included in the base sequence determination is defined as: a second biochemical reaction—a first biochemical reaction—photographing. The method includes, after initiation steps are completed, using the fluid device to perform the second biochemical reaction and the first biochemical reaction of the sample on the first component, while using the optical device to photograph the sample on the second component. The initial steps include: a. using the fluid device to perform the first biochemical reaction of the sample on the first component, b. using the optical device to photograph the sample on the first component after the first biochemical reaction, and c.

Abstract: The present disclosure discloses a method and a system for imaging. The method for imaging objects using the system for imaging. The system for imaging comprises a lens. The objects comprise a first object, a second object and a third object located at different positions on a first preset track. The method for imaging comprises: allowing the lens and the first preset track to move relatively in a first predetermined relationship to acquire a clear image of the third object using the system for imaging without focusing, the first predetermined relationship is determined by a focal plane position of the first object and a focal plane position of the second object. The aforementioned method for imaging is high in imaging efficiency and is capable of fast focusing according to the first predetermined relationship even if focus tracking fails so that the blurring of a photographed image due to defocusing is avoided.

Abstract: Disclosed are a positioning method, a positioning apparatus and a sequencing system (300). The sequencing system (300) comprises an imaging assembly (110) and a mobile platform (102), wherein the imaging assembly (110) comprises an optical axis (OP), the mobile platform (102) bears a reaction apparatus (200), the stroke of the mobile platform (102) in a first direction is controlled by means of a limiting switch, and the stroke comprises a first limit.

Abstract: The present disclosure relates to base sequence determination. A base sequence determination system includes a fluid device and an optical device, a reaction device includes a first component and a second component, and a repeated executable unit is defined as: a second biochemical reaction—a first biochemical reaction—photographing. A method includes, after initiation steps, using the fluid device to perform the second biochemical reaction and the first biochemical reaction of the sample on the first component, while using the optical device to photograph the sample on the second component. The initial steps include: using the fluid device to perform the first biochemical reaction of the sample on the first component, using the optical device to photograph the sample on the first component after the first biochemical reaction, and using the fluid device to perform the first biochemical reaction of the sample on the second component.