Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device, including a function level reset manager. The function level reset manager can receive a function level reset request from a host system, generate a function level reset bitmap based on the function level reset request, and broadcast the function level reset request to a command processing pipeline. The function level reset bitmap can indicate which functions are in a reset state. Further, the function level reset manager can determine which functions are in the reset state and instruct the command processing pipeline to cancel commands associated with the functions in the reset state.

Abstract: A technique for sharing resources in a data storage device. The data storage device receives a command associated with a non-volatile semiconductor memory device from a host system, the command including a virtual function identifier and a transaction identifier. The data storage device identifies, via a virtual function mapping unit that is included within a controller and that maintains a function mapping table which stores programmable values that associate virtual functions with portions of shared resources of the controller, a portion of a shared resource of the controller based on the virtual function identifier and the transaction identifier. The data storage device accesses the identified portion of the shared resource based on the received command.

Abstract: A technique for sharing resources in a data storage device. The data storage device receives a command associated with a non-volatile semiconductor memory device from a host system, the command including a virtual function identifier and a transaction identifier. The data storage device identifies, via a virtual function mapping unit that is included within a controller and that maintains a function mapping table which stores programmable values that associate virtual functions with portions of shared resources of the controller, a portion of a shared resource of the controller based on the virtual function identifier and the transaction identifier. The data storage device accesses the identified portion of the shared resource based on the received command.

Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device, including a function level reset manager. The function level reset manager can receive a function level reset request from a host system, generate a function level reset bitmap based on the function level reset request, and broadcast the function level reset request to a command processing pipeline. The function level reset bitmap can indicate which functions are in a reset state. Further, the function level reset manager can determine which functions are in the reset state and instruct the command processing pipeline to cancel commands associated with the functions in the reset state.

Abstract: Described herein is a chip-based apparatus for amplifying nucleic acids, a cartridge housing the apparatus, and methods of using the apparatus for amplification of nucleic acids. More specifically, this invention provides integrated semiconductor chip, manufactured with standard semiconductor manufacturing process, with on-chip circuitry to perform thermal management and optical sensing necessary for amplification of nucleic acids. The apparatus and methods embodied in this invention makes it possible to build a disease diagnosis and prognosis tool that is easy to use, portable and disposable.

Abstract: A core-inlaid high manganese steel frog structure includes a high manganese steel frog body and an inlaid core. The high manganese steel frog body includes a swing track connecting section, a frog central section and a frog-and-track connecting section. The wing track connecting section and the frog-and-track connecting section are respectively arranged on front and rear ends of the frog central section. A mounting groove for cooperatively mounting the inlaid core is arranged in front of the frog central section. The high manganese steel frog body and the inlaid core are detachably connected. The high manganese steel frog body and the inlaid core are detachably connected, which facilitates replacement of vulnerable parts, saves cost, and meets user requirements. The material and production procedure for the high-manganese steel frog body can be different from those for the inlaid core, which helps further improve the performance of the inlaid core.

Abstract: A technique for sharing resources in a data storage device. The data storage device receives a command associated with a non-volatile semiconductor memory device from a host system, the command including a virtual function identifier and a transaction identifier. The data storage device identifies, via a virtual function mapping unit that is included within a controller and that maintains a function mapping table which stores programmable values that associate virtual functions with portions of shared resources of the controller, a portion of a shared resource of the controller based on the virtual function identifier and the transaction identifier. The data storage device accesses the identified portion of the shared resource based on the received command.

Abstract: Described herein is a chip-based apparatus for amplifying nucleic acids, a cartridge housing the apparatus, and methods of using the apparatus for amplification of nucleic acids. More specifically, this invention provides integrated semiconductor chip, manufactured with standard semiconductor manufacturing process, with on-chip circuitry to perform thermal management and optical sensing necessary for amplification of nucleic acids. The apparatus and methods embodied in this invention makes it possible to build a disease diagnosis and prognosis tool that is easy to use, portable and disposable.

Abstract: A technique for sharing resources in a data storage device. The data storage device receives a command associated with a non-volatile semiconductor memory device from a host system, the command including a virtual function identifier and a transaction identifier. The data storage device identifies, via a virtual function mapping unit that is included within a controller and that maintains a function mapping table which stores programmable values that associate virtual functions with portions of shared resources of the controller, a portion of a shared resource of the controller based on the virtual function identifier and the transaction identifier. The data storage device accesses the identified portion of the shared resource based on the received command.

Abstract: Described herein is a chip-based apparatus for amplifying nucleic acids, a cartridge housing the apparatus, and methods of using the apparatus for amplification of nucleic acids. More specifically, this invention provides integrated semiconductor chip, manufactured with standard semiconductor manufacturing process, with on-chip circuitry to perform thermal management and optical sensing necessary for amplification of nucleic acids. The apparatus and methods embodied in this invention makes it possible to build a disease diagnosis and prognosis tool that is easy to use, portable and disposable.

Abstract: Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

Abstract: A secure removable card has electrical connections for communication therewith. The card comprises a first integrated circuit die, with the first die including a processor. The card has a second integrated circuit die, with the second die including a non-volatile memory for storing a secret key, and a controller for controlling the operation of the non-volatile memory. A bus connects the first die with the second die. The processor can generate a key pair, having a public key portion and a private key portion upon power up, and transfers the public key portion across the bus to the second die. The controller can receive the public key and encrypt the secret key with the public key to generate a first encrypted key, and can transfer the first encrypted key across the bus to the first die.

Abstract: Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

Abstract: A secure removable card has electrical connections for communication therewith. The card comprises a first integrated circuit die, with the first die including a processor. The card has a second integrated circuit die, with the second die including a non-volatile memory for storing a secret key, and a controller for controlling the operation of the non-volatile memory. A bus connects the first die with the second die. The processor can generate a key pair, having a public key portion and a private key portion upon power up, and transfers the public key portion across the bus to the second die. The controller can receive the public key and encrypt the secret key with the public key to generate a first encrypted key, and can transfer the first encrypted key across the bus to the first die.

Abstract: A removable card for use with a mobile wireless communication device has a processor and a non-volatile memory, connected to the processor. The memory has programming code stored configured to be executed by the processor and is operable in one of two modes. In a first mode the card is connected to the device with the card storing information received wirelessly by the device from the Internet. In a second mode the card is connected to a network portal device, which is connected to the Internet, with the card storing information received through the network portal device from the Internet. In another embodiment, the removable card has electrical connections for connecting to a mobile wireless communicating device for use by a user to connect to the Internet. The memory has two portions: a first portion and a second portion with the partitioning being alterable. The processor restricts access to the first portion by the user, while grants access to the second portion to the user.

Abstract: All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers, a read access involves multiplexing out of appropriate data for the pointer address from these pointer registers to form a target pointer address.

Abstract: An integrated circuit device has a processing unit, a memory management unit, and a memory. The memory management unit is interposed between the memory and the processing unit for controlling access to the memory by the processing unit in one of three modes. In a first mode, called the system mode, the processing unit can access a system program stored in the memory for controlling the resources of the integrated circuit device. In a second mode, called the kernel mode, the processing unit can access an operating system program stored in the memory for controlling the of the integrated circuit device, limited by the system program. Finally in a third mode, called the user mode, the processing unit can access an application program stored in the memory for controlling the resources of the integrated circuit device, limited by the operating system program.

Abstract: All Pointer-based accesses require first that the value contained in a pointer register (200a, 200b, 200c, 200d) to be read and then that value be used as an address to the appropriate region in random access memory (RAM) (104). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory (103a, 103b, 103c, 103d) to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers (200a, 200b, 200c, 200d), a read access involves mutliplexing out of appropriate data for the pointer address from these pointer registers (200a, 200b, 200c, 200d) to form a target pointer address.

Abstract: Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register contents and other critical first program stream data does not occur, the processor (180) has no way of knowing whether the first program stream data restored to the registers has become corrupt or not. Thus, a novel register architecture (120, 121, 122, 123, 124, 125) is provided that facilitate processing of interrupting program streams without storing and restoring interrupted program stream critical data.

Abstract: A multi-mode architecture is disclosed for a semiconductor circuit, such as a smart card, microcontroller or another single-chip data processing circuit. The disclosed semiconductor circuit supports at least two modes of operation. A memory management unit restricts each application to a predetermined memory range and enforces certain mode-specific restrictions for each memory partition. In a secure kernel mode, all resources and services on the semiconductor circuit, such as special function registers, are accessible. In an application mode, certain special function registers are not accessible (and thus, the resources associated with such special function registers are also not accessible). The operating system is normally executed in a secure kernel mode, where most, if not all resources are accessible. Likewise, a user application is normally executed in a user mode, where certain resources are not accessible.