Patents by Inventor Zhiming Geng

Zhiming Geng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145114
    Abstract: Provided is a method for regulating a thermal boundary conductance between a metal and an insulator, including: arranging a metal on a surface of an insulator, a contact surface between the metal and the insulator being a boundary between the metal and the insulator; and the insulator including a ferroelectric, a piezoelectric, or a pyroelectric; applying an external electric field or stress to the ferroelectric, and adjusting a magnitude of the external electric field or stress, or an included angle between a direction of the external electric field or stress with the boundary to regulate the thermal boundary conductance; or applying a stress to the piezoelectric, and adjusting a magnitude of the stress, or an included angle between a direction of the stress with the boundary to regulate the thermal boundary conductancer; or adjusting a temperature of the pyroelectric to regulate the thermal boundary conductance.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 2, 2024
    Inventors: Yuefeng Nie, Yipeng Zang, Minghui Lu, Xuejun Yan, Chen Di, Zhiming Geng
  • Patent number: 11049899
    Abstract: A structure and a method for packaging an image sensor chip. The structure includes: an image sensor chip and a substrate. The image sensor chip includes a first surface and a second surface that are opposite to each other, and the first surface is provided with multiple pixels configured to collect image information and multiple first bonding pads connected with the multiple pixels. The substrate covers the first surface of the image sensor chip, and is provided with wiring and a contact terminal connected with the wiring. A periphery of the image sensor chip is bonded to the substrate via an anisotropic conductive adhesive, the multiple first bonding pads are electrically connected with the contact terminal via the anisotropic conductive adhesive, and the anisotropic conductive adhesive surrounds all the multiple pixels and is not overlapped with the multiple pixels in a direction perpendicular to the substrate.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 29, 2021
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Zhiming Geng
  • Publication number: 20200303448
    Abstract: A structure and a method for packaging an image sensor chip. The structure includes: an image sensor chip and a substrate. The image sensor chip includes a first surface and a second surface that are opposite to each other, and the first surface is provided with multiple pixels configured to collect image information and multiple first bonding pads connected with the multiple pixels. The substrate covers the first surface of the image sensor chip, and is provided with wiring and a contact terminal connected with the wiring. A periphery of the image sensor chip is bonded to the substrate via an anisotropic conductive adhesive, the multiple first bonding pads are electrically connected with the contact terminal via the anisotropic conductive adhesive, and the anisotropic conductive adhesive surrounds all the multiple pixels and is not overlapped with the multiple pixels in a direction perpendicular to the substrate.
    Type: Application
    Filed: July 6, 2018
    Publication date: September 24, 2020
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Zhiming Geng
  • Publication number: 20190259634
    Abstract: A packaging structure and a packaging method are provided. The packaging structure includes a substrate, a circuit wiring layer arranged on the substrate, a conductive bump arranged on the circuit wiring layer, and a semiconductor chip flip-chip mounted over the substrate. A functional area and a pad surrounding the functional area are arranged on a first surface of the semiconductor chip facing the substrate, and the pad is electrically connected to the conductive bump. The packaging structure further includes a sealing layer arranged on the substrate and surrounding the semiconductor chip, and a blocking structure arranged on the substrate. The blocking structure surrounds the functional area to block a material of the sealing layer from overflowing into the functional area.
    Type: Application
    Filed: June 28, 2017
    Publication date: August 22, 2019
    Applicant: China Wafer level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Zhijie Shen, Zhiming Geng, Jian Zhang