Patents by Inventor Zhinan (Peter) Wei

Zhinan (Peter) Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7633552
    Abstract: Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A first converter converts the sliced sync signal to a control signal having an amplitude or magnitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A second converter converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude or magnitude of the control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal. These timed intervals produced in accordance with embodiments of the present invention are easily and precisely scalable, allowing them to be used to discriminate various timing features embedded in video signals.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: December 15, 2009
    Assignee: Intersil Americas Inc.
    Inventors: Zhinan (Peter) Wei, Robert David Zucker
  • Publication number: 20080278625
    Abstract: Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A first converter converts the sliced sync signal to a control signal having an amplitude or magnitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A second converter converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude or magnitude of the control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal. These timed intervals produced in accordance with embodiments of the present invention are easily and precisely scalable, allowing them to be used to discriminate various timing features embedded in video signals.
    Type: Application
    Filed: July 21, 2008
    Publication date: November 13, 2008
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Zhinan (Peter) Wei, Robert David Zucker
  • Patent number: 7423694
    Abstract: Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A frequency-to-voltage converter converts the sliced sync signal to a voltage control signal having an amplitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A voltage-to-timed interval converter that converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude of the voltage control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: September 9, 2008
    Assignee: Intersil Americas Inc.
    Inventors: Zhinan (Peter) Wei, Robert David Zucker
  • Patent number: 6781532
    Abstract: A method and apparatus for generating reference voltages for a flat panel display system using a digital to analog converter (DAC) to supply multiple reference voltages to the flat panel display system. The DAC is adapted to accept digital input voltage reference from one of a plurality of registers and to provide an analog output to one of a plurality of sample and hold circuits. A controller selects which one of the plurality of registers is coupled to the DAC input, and selects which one of the plurality of sample and hold circuits is coupled to the DAC output.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: August 24, 2004
    Assignee: Elantec Semiconductor, Inc.
    Inventor: Zhinan (Peter) Wei