Patents by Inventor Zhinan Wei

Zhinan Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10056822
    Abstract: A control circuit for a switching regulator implementing a fixed frequency constant on-time control scheme incorporates a reference voltage generator to generate a reference voltage ramp that varies over substantially the entire switching period. In one embodiment, the reference voltage increases from an initial voltage value at the start of each switching period towards the end of the switching period and is reset to the initial voltage value at the end of each switching period. The reference voltage ramp ensures stable feedback control operation in the switching regulator without introducing voltage offset for all output voltage values. The control circuit enables the switching regulator to apply constant on-time control scheme while using an output capacitor having any ESR value, including an output capacitor with low or zero ESR.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 21, 2018
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Zhiye Zhang, Zhinan Wei
  • Patent number: 9401637
    Abstract: A switching regulator controller for a buck switching regulator incorporates a multi-mode adaptive modulator configured to automatically select between a first operation mode and a second operation mode as a function of the output voltage being generated. In one embodiment, the switching regulator controller compares the output voltage to a comparator reference voltage and is configured to operate in a selected operation mode based on the output voltage. In this manner, a single switching regulator controller can be used in multiple instances of an electronic system to supply circuitry that may have different operational requirements. In one embodiment, the switching regulator controller is configured to operation in a PWM/PFM mode and a PWM mode as a function of the output voltage, which indicates the circuit application to which the switch regulator controller is used to supply.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: July 26, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Zhinan Wei, Zhiye Zhang, Allen Chang
  • Publication number: 20140266090
    Abstract: A switching regulator controller for a buck switching regulator incorporates a multi-mode adaptive modulator configured to automatically select between a first operation mode and a second operation mode as a function of the output voltage being generated. In one embodiment, the switching regulator controller compares the output voltage to a comparator reference voltage and is configured to operate in a selected operation mode based on the output voltage. In this manner, a single switching regulator controller can be used in multiple instances of an electronic system to supply circuitry that may have different operational requirements. In one embodiment, the switching regulator controller is configured to operation in a PWM/PFM mode and a PWM mode as a function of the output voltage, which indicates the circuit application to which the switch regulator controller is used to supply.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Zhinan Wei, Zhiye Zhang, Allen Chang
  • Patent number: 7728655
    Abstract: A current limiting load switch for bridging supply Vss and load with a reference voltage VRdt dynamically generated by a VRdt-generator is proposed. It includes: A pair of power FET and sense FET interconnected in split-current configuration. The FET pair develops a load voltage while limiting load current Iload to a preset maximum Imax. The FET pair is sized to draw device currents Ipower and Is with RATIOI=Is/Ipower<<1. The sense FET high-side terminal is coupled to Vss through a sense resistor Rsense developing a sense voltage Vs=Is×Rsense. A current limiting amplifier with inputs connected to VRdt and Vs and output controlling FET pair closing a current limiting feedback loop. The VRdt-generator dynamically adjusts VRdt concurrent and compensatory with an undesirable effect of changing RATIOI caused by the sense FET operational transition thus eliminating a transitional overshoot of Iload beyond Imax.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: June 1, 2010
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Kevin Ng, Zhinan Wei, Wai-Keung Peter Cheng, Allen Chang
  • Publication number: 20100090755
    Abstract: A current limiting load switch for bridging supply Vss and load with a reference voltage VRdt dynamically generated by a VRdt-generator is proposed. It includes: A pair of power FET and sense FET interconnected in split-current configuration. The FET pair develops a load voltage while limiting load current Iload to a preset maximum Imax. The FET pair is sized to draw device currents Ipower and Is with RATIOI=Is/Ipower<<1. The sense FET high-side terminal is coupled to Vss through a sense resistor Rsense developing a sense voltage Vs=Is×Rsense. A current limiting amplifier with inputs connected to VRdt and Vs and output controlling FET pair closing a current limiting feedback loop. The VRdt-generator dynamically adjusts VRdt concurrent and compensatory with an undesirable effect of changing RATIOI caused by the sense FET operational transition thus eliminating a transitional overshoot of Iload beyond Imax.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 15, 2010
    Inventors: Kevin Ng, Zhinan Wei, Wai-Keung Peter Cheng, Allen Chang
  • Patent number: 7457092
    Abstract: A circuit and method for controlling a MOSFET based switch that includes two back-to-back FET to block current flow in the OFF state irrespective of the polarity of the voltage differential across the switch. The MOSFET based switch further has a built-in current limit function by sensing the current flow through one of the two MOSFET switches. Furthermore, the bilateral current-limited switch further includes circuitry required for controlling both P type and N type FET in either common drain or common source configuration.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: November 25, 2008
    Assignee: Alpha & Omega Semiconductor, LLD.
    Inventors: Allen Chang, Zhinan Wei
  • Publication number: 20070127182
    Abstract: A circuit and method for controlling a MOSFET based switch that includes two back-to-back FET to block current flow in the OFF state irrespective of the polarity of the voltage differential across the switch. The MOSFET based switch further has a built-in current limit function by sensing the current flow through one of the two MOSFET switches. Furthermore, the bilateral current-limited switch further includes circuitry required for controlling both P type and N type FET in either common drain or common source configuration.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 7, 2007
    Inventors: Allen Chang, Zhinan Wei
  • Publication number: 20070002174
    Abstract: Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A frequency-to-voltage converter converts the sliced sync signal to a voltage control signal having an amplitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A voltage-to-timed interval converter that converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude of the voltage control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal.
    Type: Application
    Filed: August 9, 2005
    Publication date: January 4, 2007
    Applicant: Intersil Americas Inc.
    Inventors: Zhinan Wei, Robert Zucker
  • Patent number: 6927712
    Abstract: A method and apparatus for generating reference voltages for a flat panel display system includes using a digital to analog converter (DAC) to supply multiple reference voltages to the flat panel display system, and wherein the DAC is adapted to accept digital input voltage reference from one of a plurality of registers and is adapted to provide an analog output to a demultiplexer, which includes a plurality of selectable sample and hold circuits.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: August 9, 2005
    Assignee: Elantec Semiconductor, Inc.
    Inventor: Zhinan Wei
  • Publication number: 20040257252
    Abstract: A method and apparatus for generating reference voltages for a flat panel display system includes using a digital to analog converter (DAC) to supply multiple reference voltages to the flat panel display system, and wherein the DAC is adapted to accept digital input voltage reference from one of a plurality of registers and is adapted to provide an analog output to a demultiplexer, which includes a plurality of selectable sample and hold circuits.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 23, 2004
    Applicant: Elantec Semiconductor, Inc.
    Inventor: Zhinan Wei
  • Publication number: 20030043060
    Abstract: A method and apparatus for generating reference voltages for a flat panel display system comprising using a digital to analog converter (DAC) 12 to supply multiple reference voltages to the flat panel display system, and wherein the DAC 12 is adapted to accept digital input voltage reference from one of a plurality of registers 14 and is adapted to provide an analog output to one of a plurality of sample and hold circuits 18. A controller 16 selects which one of the plurality of registers 14 is coupled to the DAC 12 input, and selects which one of the plurality of sample and hold circuits 18 is coupled to the DAC 12 output.
    Type: Application
    Filed: September 5, 2002
    Publication date: March 6, 2003
    Inventor: Zhinan Wei