Abstract: An array substrate, a method of manufacturing the array substrate, and a display device are disclosed, for eliminating white Mura defects generated during the Cell process. The method comprises steps of: forming a display area and a non-display area on a substrate, a circuit bonding area being arranged within the non-display area; forming an alignment film within the display area through a patterning process; forming, through a patterning process, a transparent protection layer at least in a portion of the non-display area other than the circuit bonding area; and forming, through a rubbing-imprinting process, a plurality of lines having the same orientation on a surface of the alignment film, for an ordered arrangement of liquid crystal molecules, wherein a surface height of the transparent protection layer is lower than or equal to a surface height of the alignment film.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a subpixel, a black matrix arranged around the subpixel, and a spacer arranged on the black matrix. At least a portion of the black matrix includes a primary region and a secondary region, one of which is arranged between two adjacent subpixels in an alignment rubbing direction. The spacer is arranged on the primary region, and an alignment rubbing shadow is shielded by the primary region.

Abstract: The present invention provides a display substrate, a mother substrate for display substrates and a display device. The display substrate comprises a display area and a non-display area surrounding the display area, wherein an alignment layer is disposed in the display area and the non-display area. In the display substrate according to the present invention, by providing the same pattern of alignment layer in both of the non-display area and the display area of the display substrate, the Mura defect caused by the difference of surface roughness between the display area and the non-display area of the display substrate may be significantly reduced, and a large amount of small foreign matters gathered due to the rubbing between the rubbing cloth and metal residuals may also be significantly reduced. Therefore, the yield of production and the quality of products may be improved.

Abstract: An array substrate comprises data lines, gate lines, thin film transistors and pixel electrodes formed on a base substrate. Pixel units are defined by intersecting the data lines and the gate lines, the thin film transistors are formed at the intersections of the data lines and the gate lines, and the data lines extend across each of the pixel units in the middle of the pixel units. At least two thin film transistors for controlling a same pixel electrode are respectively formed on both sides of the data line in each pixel unit.

Abstract: An array substrate comprises data lines, gate lines, thin film transistors and pixel electrodes formed on a base substrate. Pixel units are defined by intersecting the data lines and the gate lines, the thin film transistors are formed at the intersections of the data lines and the gate lines, and the data lines extend across each of the pixel units in the middle of the pixel units. At least two thin film transistors for controlling a same pixel electrode are respectively formed on both sides of the data line in each pixel unit.

Abstract: An array substrate comprises data lines, gate lines, thin film transistors and pixel electrodes formed on a base substrate. Pixel units are defined by intersecting the data lines and the gate lines, the thin film transistors are formed at the intersections of the data lines and the gate lines, and the data lines extend across each of the pixel units in the middle of the pixel units. At least two thin film transistors for controlling a same pixel electrode are respectively formed on both sides of the data line in each pixel unit.

Abstract: An array substrate comprises data lines, gate lines, thin film transistors and pixel electrodes formed on a base substrate. Pixel units are defined by intersecting the data lines and the gate lines, the thin film transistors are formed at the intersections of the data lines and the gate lines, and the data lines extend across each of the pixel units in the middle of the pixel units. At least two thin film transistors for controlling a same pixel electrode are respectively formed on both sides of the data line in each pixel unit.