Abstract: A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

Abstract: A host interface controller having a first buffer set and a second buffer set operated in a ping-pong buffer mode by a control module to alternately work as a pre-fetch buffer set. When one buffer set between the first buffer set and the second buffer set works as the pre-fetch buffer set, the control module pre-fetches and buffers data starting from a first address of a storage device into the pre-fetch buffer set and accesses the other buffer set between the first buffer set and the second buffer set to respond to a read request that the central processing unit issues to access data of a second address of the storage device.

Abstract: A host controller with suppressed data jitter is shown, which uses a logical physical layer (LPHY) to provide groups of low-speed data, uses a clock-domain-crossing transmitter (TXCDC) to transmit the groups of the low-speed data to the corresponding electrical physical layers (EPHYs), uses the EPHYs to convert the groups of the low-speed data to high-speed data and transmit the high-speed data to the corresponding external devices, and further has a multiplexer. Each EPHY corresponds to one clock signal and operates accordingly. The multiplexer receives the clock signals of the EPHYs to output a common clock signal for the LPHY to provide the groups of low-speed data and for the TXCDC to retrieve the groups of low-speed data. With respect to each of the external devices, the TXCDC uses the clock signal corresponding to the corresponding EPHY to output the corresponding group of low-speed data to the corresponding EPHY.

Abstract: A peripheral interface circuit at host side and an electronic system using the same is disclosed. The peripheral interface circuit has a bus clock signal generator and a data register. The bus clock signal generator outputs a bus clock signal based on a host clock signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data. The data register receives the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal. The bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal.

Abstract: A computer system is provided. In one embodiment, the computer system includes a memory, a peripheral device, a central processing unit (CPU), and a peripheral device controller. The CPU stores information about the data transmission in a descriptor in the memory when data transmission between the CPU and the peripheral device is required. The peripheral device controller reads the descriptor from the memory at an access frequency, records whether the descriptor read from the memory requests for data transmission as a recording result, and adjusts the access frequency according to the recording result.

Abstract: A USB host controller is provided. The USB host controller is capable of communicating with multiple USB apparatuses having endpoints and sends a request to a first endpoint. The USB host controller includes a first storage and a first control unit. The first control unit stores endpoint information from the first endpoint into the first storage when the first endpoint issues an unready transaction packet in response to the request. The unready transaction packet indicates that the first endpoint is not ready.

Abstract: A USB host control method is provided for a USB host controller. The USB host controller includes a USB device and a buffer, the USB device includes one or more endpoints. The USB host control method includes the steps of: storing first output data to be sent to a first endpoint into one or more buffer units used for the first endpoint; sending the first output data to the first endpoint; and when a first predetermined response from the first endpoint is received, configuring fake releasing labels and information tags corresponding to the first endpoint in the one or more buffer units, and not releasing the one or more buffer units.

Abstract: A host module is disclosed, in which an interface is used to couple to at least an electronic device through a serial bus and comprises at least first and second ports. A detection unit reports that one of the first and second ports is enabled and the other is not enabled to a serial bus host driver and enables the interface to perform data transmission with the electronic device connected to the first and second ports through two parallel transmission channels of the serial bus, when the first and second ports are both connected to the same electronic device through the serial bus.

Abstract: A USB host control method is provided for a USB host controller. The USB host controller includes a USB device and a buffer, the USB device includes one or more endpoints. The USB host control method includes the steps of: storing first output data to be sent to a first endpoint into one or more buffer units used for the first endpoint; sending the first output data to the first endpoint; and when a first predetermined response from the first endpoint is received, configuring fake releasing labels and information tags corresponding to the first endpoint in the one or more buffer units, and not releasing the one or more buffer units.

Abstract: A USB host controller is provided. The USB host controller is capable of communicating with multiple USB apparatuses having endpoints and sends a request to a first endpoint. The USB host controller includes a first storage and a first control unit. The first control unit stores endpoint information from the first endpoint into the first storage when the first endpoint issues an unready transaction packet in response to the request. The unready transaction packet indicates that the first endpoint is not ready.

Abstract: A host module is disclosed, in which an interface is used to couple to at least an electronic device through a serial bus and comprises at least first and second ports. A detection unit reports that one of the first and second ports is enabled and the other is not enabled to a serial bus host driver and enables the interface to perform data transmission with the electronic device connected to the first and second ports through two parallel transmission channels of the serial bus, when the first and second ports are both connected to the same electronic device through the serial bus.

Abstract: A computer system is provided. In one embodiment, the computer system includes a memory, a peripheral device, a central processing unit (CPU), and a peripheral device controller. The CPU stores information about the data transmission in a descriptor in the memory when data transmission between the CPU and the peripheral device is required. The peripheral device controller reads the descriptor from the memory at an access frequency, records whether the descriptor read from the memory requests for data transmission as a recording result, and adjusts the access frequency according to the recording result.