Patents by Inventor Zhiqiang J. Su

Zhiqiang J. Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to detect NAND-flash parameters by hardware automatically
    Patent number: 7657696
    Abstract: A method for automatically detecting a plurality of parameters for a NAND-Flash memory. A first step of the method may include generating a plurality of address cycles for the NAND-Flash memory. A second step may set an address number parameter of the parameters based on (i) a first number of the address cycles generated and (ii) a status signal generated by the NAND-Flash memory responsive to the address cycles. A third step generally includes generating at least one read cycle for the NAND-Flash memory after determining the address number parameter. A fourth step may set a page size parameter of the parameters based on (i) a second number of the read cycles generated and (ii) the status signal further responsive to the read cycles.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 2, 2010
    Assignee: LSI Corporation
    Inventors: Zhiqiang J. Su, Qasim R. Shami, Hongping Liu, Hui Lan
  • Multi-level register bank based configurable ethernet frame parser
    Patent number: 7292572
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of match signals in response to an incoming data signal. Each match signal is generated in response to different search criteria. The second circuit may be configured to present a protocol indication signal in response to the plurality of match signals.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: November 6, 2007
    Assignee: LSI Corporation
    Inventors: Hongping Liu, Zhiqiang J. Su
  • Multi-level register bank based configurable etherner frame parser
    Publication number: 20040125807
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of match signals in response to an incoming data signal. Each match signal is generated in response to different search criteria. The second circuit may be configured to present a protocol indication signal in response to the plurality of match signals.
    Type: Application
    Filed: December 11, 2002
    Publication date: July 1, 2004
    Applicant: LSI LOGIC CORPORATION
    Inventors: Hongping Liu, Zhiqiang J. Su