Abstract: A method for using a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor. For each of the read requests, a determination is made as to whether there is a cache line hit corresponding to the request. For each cache line miss, a cache line slot is allocated to store a new cache line responsive to the cache line miss. An in-order set of cache lines is output to the video processor responsive to the queue of read requests.

Abstract: A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor, and tracking each of a plurality of cache lines stored within the cache using a least recently used variable. For each a cache line hit out of the plurality of cache lines and corresponding to one of the read requests, the least recently used variable is adjusted for a remainder of the plurality of cache lines. A replacement cache line is determined by examining the least recently used variables for each of the plurality of cache lines. For each cache line miss, a cache line slot corresponding to the replacement cache line is allocated to store a new cache line responsive to the cache line miss.

Abstract: A memory system, method, and computer program product are provided. In use, a plurality of portions of memory is arranged contiguously. Further, a number of requests required to retrieve the portions of memory is reduced utilizing the arrangement. In one possible embodiment, such technique may be used in the context of film grain technology (FGT), such that the portions of memory include portions of a film grain image stored in a film grain database (FGDB).