Patents by Inventor Zhi Qiang Niu
Zhi Qiang Niu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11258270Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.Type: GrantFiled: June 28, 2019Date of Patent: February 22, 2022Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
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Publication number: 20200412148Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
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Patent number: 10818568Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.Type: GrantFiled: June 28, 2019Date of Patent: October 27, 2020Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
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Patent number: 10630080Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.Type: GrantFiled: June 28, 2019Date of Patent: April 21, 2020Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
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Patent number: 9337131Abstract: An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.Type: GrantFiled: September 29, 2014Date of Patent: May 10, 2016Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Yan Huo, Hamza Yilmaz, Jun Lu, Ming-Chen Lu, Zhi Qiang Niu, Yan Xun Xue, Demei Gong
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Publication number: 20160093560Abstract: An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Yan Huo, Hamza Yilmaz, Jun Lu, Ming-Chen Lu, Zhi Qiang Niu, Yan Xun Xue, Demei Gong
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Patent number: 9245831Abstract: A semiconductor package includes a lead frame having a die paddle and a plurality of leads connected to die paddle, where each lead has a lead surface parallel to die paddle and is a continuous extension bending upward from die paddle. A semiconductor chip is mounted on die paddle, where drain metal layer covering a first surface of chip is connected to die paddle, and source metal layer and gate metal layer are located on a second surface opposite to first surface with gate metal layer located at one corner of the second surface. A source metal plate and a gate metal plate are attached on source metal layer and gate metal layer respectively. A molding layer covers lead frame, semiconductor chip, source metal plate and gate metal plate, where lead surface, top surfaces of source metal plate and gate metal plate are exposed from top surface of molding layer.Type: GrantFiled: November 5, 2014Date of Patent: January 26, 2016Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Yan Huo, Zhi Qiang Niu, Ming-Chen Lu, Hongtao Gao
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Publication number: 20150171000Abstract: The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arraged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Inventors: Zhi Qiang Niu, Hamza Yilmaz, Jun Lu, Fei Wang
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Patent number: 9041172Abstract: The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.Type: GrantFiled: December 13, 2013Date of Patent: May 26, 2015Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Zhi Qiang Niu, Hamza Yilmaz, Jun Lu, Fei Wang
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Patent number: 8952509Abstract: The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.Type: GrantFiled: September 19, 2013Date of Patent: February 10, 2015Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Hamza Yilmaz, Yueh-Se Ho, Yan Xun Xue, Jun Lu, Xiaotian Zhang, Zhi Qiang Niu, Ming-Chen Lu, Liang Zhao, YuPing Gong, GuoFeng Lian
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Publication number: 20130273697Abstract: This invention discloses a mixed alloy lead frame for power semiconductor devices, which includes a plurality of heat sinks and a pin array; the heat sinks are made of the first material, with positioning holes on their upper parts and welding zones at the center of their lower parts, while the pin array is made of the second material, which is different from the first material, with a plurality of sets of terminals leading out from its upper end and lower end respectively. The heat sinks are positioned on the lead frame assembly welding plate, the pin is positioned in the area between the upper heat sinks and lower heat sinks on the lead frame assembly welding plate. The mixed alloy lead frame for power semiconductor devices in this invention improves the heat dissipation of lead frame, reduces the fabrication cost of lead frame, and enhances the flexibility of fabrication.Type: ApplicationFiled: June 10, 2013Publication date: October 17, 2013Inventors: Zhi Qiang Niu, Jun Lu, Tao Feng
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Publication number: 20110073999Abstract: This invention discloses a mixed alloy lead frame for power semiconductor devices, which includes a plurality of heat sinks and a pin array; the heat sinks are made of the first material, with positioning holes on their upper parts and welding zones at the center of their lower parts, while the pin array is made of the second material, which is different from the first material, with a plurality of sets of terminals leading out from its upper end and lower end respectively. The heat sinks are positioned on the lead frame assembly welding plate, the pin is positioned in the area between the upper heat sinks and lower heat sinks on the lead frame assembly welding plate. The mixed alloy lead frame for power semiconductor devices in this invention improves the heat dissipation of lead frame, reduces the fabrication cost of lead frame, and enhances the flexibility of fabrication.Type: ApplicationFiled: January 6, 2010Publication date: March 31, 2011Inventors: Zhi Qiang Niu, Jun Lu, Tao Feng