Patents by Inventor Zhiqiang Qin

Zhiqiang Qin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11782645
    Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: October 10, 2023
    Assignee: INTEL CORPORATION
    Inventors: Zhi Yong Chen, Zhiqiang Qin, Xueyan Wang, Fang Yuan
  • Patent number: 11354135
    Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: June 7, 2022
    Assignee: INTEL CORPORATION
    Inventors: Zhiqiang Qin, Tao Xu, Qing Huang
  • Publication number: 20220129205
    Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.
    Type: Application
    Filed: January 5, 2022
    Publication date: April 28, 2022
    Applicant: INTEL CORPORATION
    Inventors: Zhi Yong CHEN, Zhiqiang QIN, Xueyan WANG, Fang YUAN
  • Patent number: 11288010
    Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 29, 2022
    Assignee: INTEL CORPORATION
    Inventors: Zhi Yong Chen, Zhiqiang Qin, Xueyan Wang, Fang Yuan
  • Publication number: 20220053756
    Abstract: The invention discloses a chip carrier for single sperm or extremely small amount of sperms, comprising a chip carrier, an X indicator axis, a Y indicator axis, and microarrays; the chip carrier is composed of a coating layer, a polymeric material layer and specific antibodies adsorbed on the coating layer; the polymeric material layer is located at the bottom of the chip carrier; the upper surface of the polymeric material layer is attached to the lower surface of the coating layer; the coating layer is provided with several microarrays. Single sperm or extremely small amount of sperms can be stored which realizes the effective storage of single sperm or extremely small amount of sperms, to avoid cross-contamination; in addition, precise access to sperm can be realized, and the maneuverability is very strong, which can solve the requirement of cryopreservation of sperm in patients with very few sperms.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 24, 2022
    Inventors: Zhilei MAO, Yurui CHE, Keliang ZHANG, Jun ZHOU, Li CHEN, Zhiqiang QIN, Lina ZHANG
  • Publication number: 20210022340
    Abstract: The present invention relates to use of a pyridine urea compound having snail-killing activities, and relates to a method for preparing the pyridine urea compound. In particular, the present invention discloses a compound having the structure as shown in formula (I), an optical isomer thereof, a racemate thereof, a solvate thereof, or a pharmaceutically acceptable salt thereof, the compound having a significant killing effect on various snails as parasitic disease vectors and low toxicity to non-target organism fish.
    Type: Application
    Filed: August 30, 2018
    Publication date: January 28, 2021
    Inventors: Liping DUAN, Shizhu LI, Weisi WANG, Haobing ZHANG, Chunli CAO, Junmin YAO, Zhiqiang QIN, Yi TAO
  • Patent number: 10831216
    Abstract: Apparatus, method and storage medium associated with UAV position estimation are disclosed herein. In embodiments, an UAV may comprise a transmitter-receiver arrangement to transmit and receive communication signals, including receipt of absolute positioning system (APS) signals from one or more APS sensors, and wireless signals from one or more proximately located other UAVs; one or more motors or engines to provide propulsive force for the UAV; and a flight controller coupled to the transmitter-receiver arrangement and the one or more motors or engines to control at least the one or more motors or engines to provide propulsive force to navigate the UAV, based at least in part on the APS and relative positioning signals. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Ke Han, Zhen Zhou, Guangyu Ren, Zhiqiang Qin
  • Publication number: 20200249957
    Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.
    Type: Application
    Filed: December 25, 2017
    Publication date: August 6, 2020
    Applicant: INTEL CORPORATION
    Inventors: Zhiqiang Qin, Tao Xu, Qing Huang
  • Publication number: 20200218471
    Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.
    Type: Application
    Filed: September 25, 2017
    Publication date: July 9, 2020
    Applicant: INTEL CORPORATION
    Inventors: Zhi Yong CHEN, Zhiqiang QIN, Xueyan WANG, Fang YUAN
  • Publication number: 20200033888
    Abstract: Apparatus, method and storage medium associated with UAV position estimation are disclosed herein. In embodiments, an UAV may comprise a transmitter-receiver arrangement to transmit and receive communication signals, including receipt of absolute positioning system (APS) signals from one or more APS sensors, and wireless signals from one or more proximately located other UAVs; one or more motors or engines to provide propulsive force for the UAV; and a flight controller coupled to the transmitter-receiver arrangement and the one or more motors or engines to control at least the one or more motors or engines to provide propulsive force to navigate the UAV, based at least in part on the APS and relative positioning signals. Other embodiments may be disclosed or claimed.
    Type: Application
    Filed: December 22, 2016
    Publication date: January 30, 2020
    Inventors: Ke HAN, Zhen ZHOU, Guangyu REN, Zhiqiang QIN
  • Patent number: 8984287
    Abstract: A wireless personal area network access method based on the primitive, includes: a coordinator broadcasts a beacon frame to the device which requests connecting to the wireless personal area network (WPAN), the beacon frame includes the authentication request information for the device and the authentication and a key management tool supported by the coordinator; the device authenticates the authentication request information, when the coordinator has an authentication request to the device, the coordinator and the device execute the authentication based on the primitive and obtains the conversation key.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: March 17, 2015
    Assignee: China Iwncomm Co., Ltd.
    Inventors: Yuelei Xiao, Jun Cao, Xiaolong Lai, Zhenhai Huang, Bianling Zhang, Zhiqiang Qin, Qizhu Song
  • Patent number: 8631232
    Abstract: A wireless personal area network accessing method is provided, the method includes that: a coordinator broadcasts a beacon frame, the beacon frame includes the information about whether the coordinator sends an authentication requirement, the beacon frame also includes the authentication supported by the coordinator and key management package when a device receipts the authentication requirement, the device receives the beacon frame, the authentication between the coordinator and the device is made by using a authentication method corresponding to the authentication supported by the coordinator and key management package, when the device determines that the coordinator and the device is directly made according to the authentication result, or the association between the coordinator and the device is made after making session key negotiation.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: January 14, 2014
    Assignee: China Iwncomm Co., Ltd.
    Inventors: Yuelei Xiao, Jun Cao, Xiaolong Lai, Zhenhai Huang, Bianling Zhang, Zhiqiang Qin, Qizhu Song
  • Publication number: 20110055554
    Abstract: A wireless personal area network accessing method is provided, the method includes that: a coordinator broadcasts a beacon frame, the beacon frame includes the information about whether the coordinator sends an authentication requirement, the beacon frame also includes the authentication supported by the coordinator and key management package when a device receipts the authentication requirement, the device receives the beacon frame, the authentication between the coordinator and the device is made by using a authentication method corresponding to the authentication supported by the coordinator and key management package, when the device determines that the coordinator and the device is directly made according to the authentication result, or the association between the coordinator and the device is made after making session key negotiation.
    Type: Application
    Filed: January 14, 2009
    Publication date: March 3, 2011
    Applicant: CHINA IWNCOMM CO., LTD.
    Inventors: Yuelei Xiao, Jun Cao, Xiaolong Lai, Zhenhai Huang, Bianling Zhang, Zhiqiang Qin, Qizhu Song
  • Publication number: 20110029776
    Abstract: A wireless personal area network access method based on the primitive, includes: a coordinator broadcasts a beacon frame to the device which requests connecting to the wireless personal area network (WPAN), the beacon frame includes the authentication request information for the device and the authentication and a key management tool supported by the coordinator; the device authenticates the authentication request information, when the coordinator has an authentication request to the device, the coordinator and the device execute the authentication based on the primitive and obtains the conversation key.
    Type: Application
    Filed: January 14, 2009
    Publication date: February 3, 2011
    Applicant: CHINA IWNCOMM CO., LTD.
    Inventors: Yuelei Xiao, Jun Cao, Xiaolong Lai, Zhenhai Huang, Bianling Zhang, Zhiqiang Qin, Qizhu Song