Abstract: A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

Abstract: A regeneration circuit includes a first inverting circuit, a second inverting circuit, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit. The regeneration circuit also includes a third transistor including a gate coupled to a gate of the first transistor, a first switch configured to couple the third transistor to the input of the second inverting circuit based on a voltage of the first inverting circuit, a fourth transistor including a gate coupled to a gate of the second transistor, and a second switch configured to couple the fourth transistor to the input of the first inverting circuit based on a voltage of the second inverting circuit.

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

Abstract: Approaches presented herein can utilize a network that learns to embed three-dimensional (3D) coordinates on a surface of one or more 3D shapes into an aligned two-dimensional (2D) texture space, where corresponding parts of different 3D shapes can be mapped to the same location in a texture image. Alignment can be performed using a texture alignment module that generates a set of basis images for synthesizing textures. A trained network can generate a basis shared by all shape textures, and can predict input-specific coefficients to construct the output texture for each shape as a linear combination of the basis images, then deform the texture to match the pose of the input. Such an approach can ensure alignment of textures, even in situations with at least somewhat limited network capacity. To unwrap shapes of complex structure or topology, a masking network can be utilized that cuts the shape into multiple pieces to reduce the distortion in the 2D mapping.

Abstract: A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

Abstract: A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit, a third transistor and a fourth transistor. A gate of the first transistor and a gate of the fourth transistor are coupled to a first input, and a gate of the second transistor and a gate of the fourth transistor are coupled to a second input. The regeneration circuit further includes a first switch and a second switch. The first switch and the third transistor are coupled in series between a first rail and the first transistor, and the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

Abstract: An unmanned aerial vehicle (UAV)-assisted hanging ring robot for live installation and grounding includes a hanging tray, a wire hanging bracket, a hanging wire, an overturning stay wire, an overturning frame, a support, an electric lock, a walking wheel, a driving motor, a workbench, a clamp seat, a puncture clamp, a tightening mechanism, a remote controller, and a controller. The hanging tray is installed at the bottom of a UAV, one end of the overturning stay wire is connected to the overturning frame, the other end thereof hangs on ground, the driving motor is installed on the overturning frame, the walking wheel is connected to the driving motor, the puncture clamp is installed on the clamp seat, the tightening mechanism is installed on the workbench, and connected to the puncture clamp, and the electric lock, tightening mechanism, driving motor, and remote controller are connected to the controller.

Abstract: A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage having a sinking current source, configured to receive an input signal and to generate a rising edge of an output signal of the delay circuit, wherein the output signal is a delayed version of the input signal. The delay circuit further includes a first P-substage having a sourcing current source, configured to receive the input signal and to generate a falling edge of the output signal, where the sinking current source and the sourcing current source are variable in response to respective ones of a plurality of bias voltages.

Abstract: In certain aspects, an apparatus includes a multiplexer having a first input, a second input, a select input, and an output, wherein the first input is configured to receive a first reference clock signal, the second input is configured to receive a second reference clock signal, and the select input is configured to receive a select signal. The multiplexer is configured to select one of the first and second reference clock signals based on the select signal, and output the selected one of the first and second reference clock signals at the output of the multiplexer. The apparatus also includes a clock driver having an input and an output, wherein the input of the clock driver is coupled to the output of the multiplexer.

Abstract: A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.

Abstract: A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.

Abstract: A transmitter is provided that includes a voltage-mode driver and a current-mode driver. The current-mode driver includes a plurality of transconductors biased by high-pass filtered versions of a differential output voltage from the voltage-mode driver.

Abstract: A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.

Abstract: An amplifier is provided that includes a differential pair of transistors configured to steer a tail current responsive to a differential input voltage. The amplifier also includes a transconductor that tranconducts high-frequency changes in the differential output voltage into a differential bias current conducted through the differential pair of transistors.

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Abstract: A transmitter is provided that includes a voltage-mode driver and a current-mode driver. The current-mode driver includes a plurality of transconductors biased by high-pass filtered versions of a differential output voltage from the voltage-mode driver.

Abstract: An amplifier is provided that includes a differential pair of transistors configured to steer a tail current responsive to a differential input voltage. The amplifier also includes a transconductor that tranconducts high-frequency changes in the differential output voltage into a differential bias current conducted through the differential pair of transistors.

Abstract: Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.

Abstract: A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.