Patents by Inventor Zhirong Feng

Zhirong Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SRAM macro test flop
    Patent number: 8181073
    Abstract: A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: May 15, 2012
    Assignee: Oracle America, Inc.
    Inventors: Ali Vahidsafa, Robert P. Masleid, Jason M. Hart, Zhirong Feng
  • SRAM MACRO TEST FLOP
    Publication number: 20110072326
    Abstract: A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.
    Type: Application
    Filed: September 23, 2009
    Publication date: March 24, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Ali Vahidsafa, Robert P. Masleid, Jason M. Hart, Zhirong Feng