Abstract: Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated with one or more cavities filled with a low-k material or air gap where a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the one or more cavities. In other embodiments fanout can be utilized to create a wider bump pitch for the local interconnect, or for the local interconnect to connect core regions of the dies. Multiple local interconnects can also be utilized to scale down electrostatic discharge.

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible.

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

Abstract: Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible.

Abstract: An inductive device is disclosed, including a first wire coupled to a first terminal and to a second terminal, a non-conductive material surrounding the first wire, and a magnetic film. The non-conductive material spans the region from the first terminal to the second terminal. The magnetic film surrounds at least a portion of the non-conductive material between the first terminal and the second terminal. The first wire has a first amount of inductance.

Abstract: Apparatus for extending process kit components lifetimes are disclosed. In some embodiments, a process kit includes: a first ring having an inner wall defining an inner diameter, an outer wall defining an outer diameter, an upper surface between the inner wall and the outer wall, and an opposing lower surface between the inner wall and the outer wall, wherein a first portion of the upper surface proximate the inner wall is concave, and wherein a second portion of the upper surface extends horizontally away from the first portion; and a second ring having an upper surface and an opposing lower surface, wherein a first portion of the lower surface is configured to rest upon the second portion of the first ring, wherein a second portion of the lower surface is convex and extends into but does not touch the concave first portion of the upper surface of the first ring.

Abstract: An inductive device is disclosed, including a first wire coupled to a first terminal and to a second terminal, a non-conductive material surrounding the first wire, and a magnetic film. The non-conductive material spans the region from the first terminal to the second terminal. The magnetic film surrounds at least a portion of the non-conductive material between the first terminal and the second terminal. The first wire has a first amount of inductance.

Abstract: Embodiments of the present disclosure include methods and apparatus for controlling titanium-tungsten (TiW) target nodule formation. In some embodiments, a target includes: a source material comprising predominantly titanium (Ti) and tungsten (W), formed from a mixture of titanium powder and tungsten powder, wherein a grain size of a predominant quantity of the titanium powder is less than or equal to a grain size of a predominant quantity of the tungsten powder.

Abstract: Embodiments of the present disclosure include methods and apparatus for controlling titanium-tungsten (TiW) target nodule formation. In some embodiments, a target includes: a source material comprising predominantly titanium (Ti) and tungsten (W), formed from a mixture of titanium powder and tungsten powder, wherein a grain size of a predominant quantity of the titanium powder is less than or equal to a grain size of a predominant quantity of the tungsten powder.

Abstract: Apparatus for extending process kit components lifetimes are disclosed. In some embodiments, a process kit includes: a first ring having an inner wall defining an inner diameter, an outer wall defining an outer diameter, an upper surface between the inner wall and the outer wall, and an opposing lower surface between the inner wall and the outer wall, wherein a first portion of the upper surface proximate the inner wall is concave, and wherein a second portion of the upper surface extends horizontally away from the first portion; and a second ring having an upper surface and an opposing lower surface, wherein a first portion of the lower surface is configured to rest upon the second portion of the first ring, wherein a second portion of the lower surface is convex and extends into but does not touch the concave first portion of the upper surface of the first ring.

Abstract: Methods for depositing materials in high aspect ratio features are disclosed herein. In some embodiments, a method of processing a substrate may include providing a substrate having an opening formed in a first surface of the substrate and extending into the substrate towards an opposing second surface of the substrate, the opening having an aspect ratio of height to width of at least 3:1, forming a barrier layer atop the first surface of the substrate and along sidewalls and a bottom surface of the opening, the barrier layer having a first thickness atop the first surface of the substrate, and forming a seed layer atop the barrier layer, wherein a ratio of the second thickness to the first thickness ranges from about 2:1 to about 5:1.

Abstract: Methods for depositing materials in high aspect ratio features are disclosed herein. In some embodiments, a method of processing a substrate may include providing a substrate having an opening formed in a first surface of the substrate and extending into the substrate towards an opposing second surface of the substrate, the opening having an aspect ratio of height to width of at least 3:1, forming a barrier layer atop the first surface of the substrate and along sidewalls and a bottom surface of the opening, the barrier layer having a first thickness atop the first surface of the substrate, and forming a seed layer atop the barrier layer, wherein a ratio of the second thickness to the first thickness ranges from about 2:1 to about 5:1.

Abstract: A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer.