Abstract: A filter radio frequency module packaging structure and a method for manufacturing same is disclosed. A first filter chip of the filter radio frequency module packaging structure comprises a chip main body and a wall structure. The wall structure, the functional surface, and a substrate together define a closed cavity, or the wall structure and the functional surface together define a closed cavity. An encapsulation material wraps the first filter chip.

Abstract: Provided are a chip interconnection package structure and method, including: forming a sacrificial pattern layer on a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer is corresponding to a sacrificial pattern of the sacrificial pattern layer in position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and making the first interconnection hole aligned and communicated with a first interconnection pin of the ch

Abstract: Disclosed is a method of manufacturing a chiplet-fine-interconnection-package structure, comprising: mounting at least two chips on a first side surface of a substrate and preparing a temporary bonding layer on the chips, preparing a plastic package layer on a second side surface of the substrate, wherein the substrate is prepared with microvias to allow plastic package materials to flow from the microvias into an area between the first side surface of the substrate and the temporary bonding layer to prepare the plastic package layer; releasing the temporary bonding layer, and bonding a silicon bridge structure on the first pin-arrays of the two adjacent chips. The solution provided by the present invention makes it unnecessary to remove the substrate in the subsequent process and to perform grinding and thinning process on the corresponding position of the plastic package layer, thus simplifying the packaging process steps and reducing the packaging cost.

Abstract: A fan-out package structure and a fabricating method therefor are provided. The structure includes an encapsulation layer; an antenna RF module assembly and electronic component(s) embedded in the encapsulation layer; a first rewiring layer on a surface of a first side of the encapsulation layer, electrically connected to at least part of the pins of the assembly and to at least part of the pins of the electronic component(s); a second rewiring layer on a surface of a second side of the encapsulation layer, electrically connected to the encapsulation layer-interconnection conductive pillars and to the conductive solder balls/bumps; and conductive solder balls/bumps on a side of the second rewiring layer away from the encapsulation layer. The assembly includes a RF substrate, and an antenna array and RF device(s) arranged thereon. The assembly is embedded in the first side. Encapsulation-layer interconnection conductive pillars are formed in the encapsulation layer.

Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.

Abstract: Disclosed are a method for manufacturing a carrier structure suitable for chiplet fine lines and a carrier structure. The method includes: preparing a temporary bonding layer on a temporary carrier, and preparing a pin interconnection layer on the temporary bonding layer, preparing at least one fine line interconnection layer on the pin interconnection layer; preparing a core layer on the at least one fine line interconnection layer with a second electrically conductive structure interconnected with the at least one fine line interconnection layer and/or the pin interconnection layer, preparing at least one build-up layer connected to the fine line interconnection layer on the core layer, and de-bonding the temporary bonding layer to obtain the carrier structure. The solutions can prepare fine lines on a carrier structure and ensure the yield of fine line interconnection lines, thus improving the manufacturability of the fine lines, carrier structure and packaging structure.

Abstract: A 3D stacked packaging structure and a manufacturing method thereof are provided. The 3D stacked packaging structure includes a bottom-layer structure and a top-layer structure stacked thereon. The bottom-layer structure and the top-layer structure each include: a substrate layer; a diamond layer grown on the substrate layer; an ion-implanted silicon wafer layer attached to the diamond layer; and a component layer provided on the silicon wafer layer, with the four layers stacked together in sequence, wherein the substrate layer of the top-layer structure is in contact with the component layer of the bottom-layer structure, and at least one through hole provided between the bottom-layer structure and the top-layer structure, extends through the component layer, the ion-implanted silicon wafer layer, the diamond layer, and the substrate layer of the top-layer structure, and extends through the component layer of the bottom-layer structure, and is filled with a conductive material.

Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.

Abstract: The present invention relates to a negative electrode material comprising a hydrogen storage alloy and a coating layer on a surface of the hydrogen storage alloy. Based on the mass of the negative electrode active material, a content of the coating layer is no less than 2 wt %. The coating layer comprises a component shown by a general formula LnFx, wherein Ln is one element selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y, and Sc. The present invention also relates to a preparation method for the above-described negative electrode material. The present invention also relates to a nickel-metal hydride secondary battery using this negative electrode material.

Abstract: A substrate bonding method includes: providing a first and a second substrate; forming, on the first substrate, a first metal micro-bump array including first metal pillar(s) formed on the first substrate and first metal nanowires formed thereon and spaced apart from each other; forming, on the second substrate, a second metal micro-bump array including second metal pillar(s) formed on the second substrate and second metal nanowires formed thereon and spaced apart from each other; pressing the first substrate onto the second substrate, such that the first and second metal micro-bump arrays are positioned and staggered with each other, forming a physically interwoven interlocking structure between the first and second metal nanowires; applying a filling material between the first and second substrates; curing the filling material to form a bonding cavity; and then performing confined heating reflux on the first and second metal micro-bump arrays in the bonding cavity.

Abstract: A chip stack packaging structure and method includes: a base chip layer, including a base chip with pins on the front surface; at least one stacked chip layer, which is formed on the base chip layer, has an inter-chip insulating layer and at least one stacked chip attached to the insulating layer and pins on the front surface, where the front surface of the stacked chip faces the front surface of the base chip; and a top insulating layer, stacked on the stacked chip layer farthest from the base chip layer. A vertical interconnection hole is formed inside the inter-chip insulating layer to allow the corresponding pins to be communicated vertically so as to be electrically connected. Inside the vertical interconnection hole, a conductive material layer is formed that makes the corresponding pins electrically connected; the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

Abstract: A filter radio frequency module packaging structure and a method for manufacturing same is disclosed. A first filter chip of the filter radio frequency module packaging structure comprises a chip main body and a wall structure. The wall structure, the functional surface, and a substrate together define a closed cavity, or the wall structure and the functional surface together define a closed cavity. An encapsulation material wraps the first filter chip.

Abstract: Embodiments of the present application relate to the technical field of semiconductors, and provide a manufacturing method for an N-polar GaN transistor structure and a semiconductor structure. A Ga-polar epitaxial functional layer is formed by depositing, a supporting substrate is formed on the epitaxial functional layer by bonding, after the epitaxial structure is inverted, a structural substrate and a buffer layer are removed, and a source, a drain, and a gate are manufactured on the side of the exposed epitaxial functional layer away from the supporting substrate, to form an N-polar GaN transistor structure.

Abstract: A packaging method and package structure for a filter chip. The packaging method includes providing a circuit substrate, covering a first surface of the circuit substrate and/or filter chip with adhesive material and forming recessed cavities or closed cavities in the adhesive material. The method further includes adhering the filter chip to the first surface of circuit substrate via the adhesive material, such that surface acoustic wave transmitting regions of the filter chip correspond to the recessed cavities or closed cavities in the adhesive material to form a gap therebetween, and encapsulating the filter chip with encapsulating material. The method further includes forming interconnecting holes extending from a second surface of the circuit substrate to pins of the filter chip, filling the interconnecting holes with conductive material, so that the conductive material is in electrical contact with a chip pin bump or pad metal of the filter chip, and forming external pin pads on the second surface.

Abstract: Provided are a chip fine line fan-out package structure and a manufacturing method therefor. The chip fine line fan-out package structure provided and the chip fine line fan-out package structure manufactured using the manufacturing method each include an inter-chip fine winding layer and a package winding layer. The line width and line spacing of the inter-chip fine winding layer are less than the line width and line spacing of the package winding layer, and therefore, a user can choose to use different package winding layers according to actual needs. Therefore, the chip fine line fan-out package structure and the package structure manufactured using the manufacturing method can meet the use demands of users in more scenarios.

Abstract: A fan-out type package and a preparation method of the fan-out type package are provided. The fan-out type package has one or more chips having same or different functions and each having a back surface mounted in a chip mounting region of the heat dissipation sheet via the adhesive material layer, and a front surface covered by a temporary protection material; an adhesive material layer; a heat dissipation sheet; an encapsulation material layer formed by making an encapsulation material flow into and fill a gap between the temporary protection material and the heat dissipation sheet and/or cover a side of the heat dissipation sheet opposite to a side thereof mounted with the chip, and then removing the temporary protection material; a packaging circuit grown on the front surface of the chip, the encapsulation material, and the heat dissipation sheet; and a packaging circuit protection layer protecting the packaging circuit.

Abstract: A chip stack packaging structure and method includes: a base chip layer, including a base chip with pins on the front surface; at least one stacked chip layer, which is formed on the base chip layer, has an inter-chip insulating layer and at least one stacked chip attached to the insulating layer and pins on the front surface, where the front surface of the stacked chip faces the front surface of the base chip; and a top insulating layer, stacked on the stacked chip layer farthest from the base chip layer. A vertical interconnection hole is formed inside the inter-chip insulating layer to allow the corresponding pins to be communicated vertically so as to be electrically connected. Inside the vertical interconnection hole, a conductive material layer is formed that makes the corresponding pins electrically connected; the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

Abstract: A touch control substrate, a preparation method thereof, a touch control module, and a display device are provided. The touch control substrate comprises: a substrate, a conductive functional layer, and a second protection medium. The conductive functional layer is arranged on one side of the substrate, and comprises patterned nano conductive structure, first protection medium, and frame lead structure. The conductive functional layer is protected by providing a two-layer protection medium structure, wherein the first protection medium fixes the structural position of the nano conductive layer and protects the partial structure of the conductive functional layer, and the second protection medium at least completely covers the nano conductive layer located in the conductive functional area; and at the same time, the touch control substrate directly disposes the frame lead layer in the peripheral area of the nano conductive layer, making the frame lead directly contacting the nano conductive layer.

Abstract: A chip packaging method and a chip packaging structure is disclosed. The method includes: attaching at least two chips to one side of substrate by adhesive layer, wherein device surface of the chip faces the substrate, and the substrate is provided therein with substrate wiring structure and/or chip; performing thinning treatment on the at least two chips provided on one side of the substrate, wherein the thinning treatment includes etching only the chips to reduce the thickness of the chips; plastically sealing the chips having undergone the thinning treatment to form a plastically sealed arrangement layer, and stacking at least two such plastically sealed arrangement layers on the substrate along plastic sealing direction; and punching the chips having undergone the thinning treatment to form first interconnection hole connecting the chips having undergone the thinning treatment to the substrate wiring structure, the chip in substrate, or the plastically sealed arrangement layer.

Abstract: Provided are a chip interconnection package structure and method, including: forming a sacrificial pattern layer on a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer is corresponding to a sacrificial pattern of the sacrificial pattern layer in position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and making the first interconnection hole aligned and communicated with a first interconnection pin of the ch