Patents by Inventor Zhiwei Cao

Zhiwei Cao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990481
    Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a backlight module. The manufacturing method of the array substrate includes: providing a base substrate; forming a metal wiring layer on a side of the base substrate, the metal wiring layer including a first copper metal layer; forming a planarization layer on a side of the metal wiring layer away from the base substrate; forming a drive lead layer on a side of the planarization layer away from the base substrate, the drive lead layer being electrically connected to the metal wiring layer, the drive lead layer including a second copper metal layer with a thickness larger than that of the first copper metal layer; forming a functional device layer on a side of the drive lead layer away from the base substrate.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 21, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhanfeng Cao, Ke Wang, Zhiwei Liang, Jianguo Wang, Guocai Zhang, Xinhong Lu, Qi Qi
  • Publication number: 20240088170
    Abstract: An array substrate including a display area having a plurality of subpixels is provided. The plurality of subpixels includes a plurality of first subpixels in a display-bonding sub-area and a plurality of second subpixels in a regular display sub-area. The array substrate includes a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels. A respective one of the plurality of first subpixels includes a bonding pad on a second side of a base substrate; a lead line electrically connecting a respective one of a plurality of thin film transistors to the bonding pad; and a via extending through the base substrate. The lead line is unexposed in the array substrate. The lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Ke Wang, Muxin Di, Zhiwei Liang, Guoqiang Wang, Renquan Gu, Xiaoxin Song, Xiaoyan Zhu, Yingwei Liu, Zhanfeng Cao
  • Patent number: 11929358
    Abstract: Provided is a display backplate including an array substrate and a plurality of pairs of connection structures on the array substrate, wherein the array substrate includes a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures and the common electrode signal line is connected to the other of the pair of connection structures; and an area of a first section of the connection structure is negatively correlated with a distance between the first section and a surface of the array substrate, and the first section is parallel to the surface of the array substrate.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: March 12, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhiwei Liang, Wenqian Luo, Yingwei Liu, Ke Wang, Qi Yao, Huijuan Wang, Haixu Li, Zhanfeng Cao, Guangcai Yuan, Xue Dong, Guoqiang Wang, Zhijun Lv
  • Publication number: 20230401044
    Abstract: Systems and methods related to generating machine code using a coroutine suspension mechanism are disclosed below. An asynchronous programming model utilizing coroutines may be implemented in a compiler for a high-level programming language. The compiler is configured to include functionality related to an intrinsic function for a suspend operation of a coroutine. In accordance with an aspect of the disclosure, a method is disclosed for generating machine code that includes the coroutine mechanism. The method includes: receiving source code for a program in a high-level programming language, and compiling the source code with a compiler to generate machine code for a target processor. The source code includes a caller and a coroutine called by the caller. The compiler is configured to detect an intrinsic function for a suspend operation in the source code for the coroutine. The compiler inserts low-level code in the machine code in accordance with an ABI.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Inventors: Konstantinos Kyriakopoulos, Michael F. Haidl, Ralf Andreas Karrenberg, Zhiwei Cao, Gokul Ramaswamy Hirisave Chandra Shekhara, Girish Bhaskarrao Bharambe, Justin Andrew Holewinski, Bharath Vasudevan
  • Patent number: 11787819
    Abstract: The present invention relates to malate salt of a multi-tyrosine kinase inhibitor. In particular, the present invention relates to crystalline forms of the malate salt of multi-tyrosine kinase inhibitor N-(3-fluoro-4-((2-(5-(((2-methoxyethyl)amino)methyl)pyridin-2-yl)thieno[3,2-b]pyridin-7-yl)oxy)phenyl)-N-(4-fluorophenyl)cyclopropane-1,1-dicarboxamide (S)-2-hydroxysuccinate (1:1), pharmaceutical compositions comprising the crystalline form, processes for preparing the crystalline form and methods of use therefore.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: October 17, 2023
    Assignee: MIRATI THERAPEPEUTICS, INC.
    Inventors: Patricia Andres, Ekaterina Albert, Emily Rigsbee, Zhiwei Cao, Dalian Zhao, Zhonghua Zhang
  • Publication number: 20220289760
    Abstract: The present invention relates to malate salt of a multi-tyrosine kinase inhibitor. In particular, the present invention relates to crystalline forms of the malate salt of multi-tyrosine kinase inhibitor N-(3-fluoro-4-((2-(5-(((2-methoxyethyl)amino)methyl)pyridin-2-yl)thieno[3,2-b]pyridin-7-yl)oxy)phenyl)-N-(4-fluorophenyl)cyclopropane-1,1-dicarboxamide (S)-2-hydroxysuccinate (1:1), pharmaceutical compositions comprising the crystalline form, processes for preparing the crystalline form and methods of use therefore.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 15, 2022
    Inventors: Patricia Andres, Ekaterina Albert, Emily Rigsbee, Zhiwei Cao, Dalian Zhao, Zhonghua Zhang
  • Publication number: 20220138435
    Abstract: The disclosure provides a method for generating a text. The method includes: obtaining a coding sequence of a first text by coding the first text; obtaining a controllable attribute of a second text to be generated; predicting a hidden state of the second text based on the coding sequence of the first text and the controllable attribute of the second text; and obtaining a second text corresponding to the first text by decoding the coding sequence of the first text based on the hidden state of the second text.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 5, 2022
    Inventors: Zhe HU, Zhiwei CAO, Jiachen LIU
  • Publication number: 20180296932
    Abstract: This invention is an amusement apparatus. In particular, a player can ride a rolling toy, for example, a bicycle or a scooter, inside a rotating tube, so the riding is emulated. The player holds controlling devices, which control the rotation speed. A multi-functional digital module is installed statically inside the tube. It can detect player's position, receive control signal, and project synchronized 3D animation in front of the player, so a virtual 3D animation is presented.
    Type: Application
    Filed: May 15, 2018
    Publication date: October 18, 2018
    Inventor: Zhiwei Cao
  • Publication number: 20180217814
    Abstract: Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like) using data tables. The single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes. SIN and COS are also computed using the pipeline according to the approximation ((?1)?IntX)*Sin(?*Min(FracX, 1.0?FracX)/Min(FracX, 1.0?FracX). A pipeline portion approximates Sin(?*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG 2(x?1)/(x?1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x?1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed. An approach for computing X?Y is also disclosed.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 2, 2018
    Inventors: Lefan Zhong, Zhiwei Cao