Abstract: A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.

Abstract: A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.

Abstract: A multiplexer device includes a plurality of selection circuits and potential setting circuits. The plurality of selection circuits respectively receive a first data signal and a second data signal, and select a corresponding one of the first data signal and the second data signal as an output signal according to the first selection signal. When the second data signal is selected as the output signal, the potential setting circuit sets a potential of a node of a first selection circuit of the plurality of selection circuits to a first voltage. The first selection circuit is configured to receive a first data signal.

Abstract: A multiplexer device includes a plurality of selection circuits and potential setting circuits. The plurality of selection circuits respectively receive a first data signal and a second data signal, and select a corresponding one of the first data signal and the second data signal as an output signal according to the first selection signal. When the second data signal is selected as the output signal, the potential setting circuit sets a potential of a node of a first selection circuit of the plurality of selection circuits to a first voltage. The first selection circuit is configured to receive a first data signal.