Abstract: An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.

Abstract: A gate quality oxide-compound semiconductor structure (10) is formed by the steps of providing a III-V compound semiconductor wafer structure (13) with an atomically ordered and chemically clean semiconductor surface in an ultra high vacuum (UHV) system (20), directing a molecular beam (26) of gallium oxide onto the surface of the wafer structure to initiate the oxide deposition, and providing a second beam (28) of atomic oxygen to form a Ga.sub.2 O.sub.3 layer (14) with low defect density on the surface of the wafer structure. The second beam of atomic oxygen is supplied upon completion of the first 1-2 monolayers of Ga.sub.2 O.sub.3. The molecular beam of gallium oxide is provided by thermal evaporation from a crystalline Ga.sub.2 O.sub.3 or gallate source, and the atomic beam of oxygen is provided by either RF or microwave plasma discharge, thermal dissociation, or a neutral electron stimulated desorption atom source.

Abstract: A method of preparing crystalline alkaline earth metal oxides on a Si substrate wherein a Si substrate with amorphous silicon dioxide on a surface is provided. The substrate is heated to a temperature in a range of 700.degree. C. to 800.degree. C. and exposed to a beam of alkaline earth metal(s) in a molecular beam epitaxy chamber at a pressure within approximately a 10.sup.-9 -10.sup.-10 Torr range. During the molecular beam epitaxy the surface is monitored by RHEED technique to determine a conversion of the amorphous silicon dioxide to a crystalline alkaline earth metal oxide. Once the alkaline earth metal oxide is formed, additional layers of material, e.g. additional thickness of an alkaline earth metal oxide, single crystal ferroelectrics or high dielectric constant oxides on silicon for non-volatile and high density memory device applications.

Abstract: A method of passivating the surface of a Si wafer is disclosed including the steps of cleaning the surface of the Si wafer and depositing an alkaline earth metal on the clean surface at a wafer temperature in a range of approximately 400.degree. C. to 750.degree. C. The surface is monitored during deposition to detect a (4.times.2) surface reconstruction pattern indicating approximately a one-quarter monolayer of alkaline earth metal is formed. The wafer is annealed at a temperature in a range of 800.degree. C. to 900.degree. C. until the alkaline earth metal forms an alkaline earth metal silicide with a (2.times.1) surface pattern on the surface.

Abstract: An electro-conductive ultraviolet light transmitting Ga.sub.2 O.sub.3 material (10) with a metallic oxide phase is deposited on a GaAs substrate or supporting structure (12). The Ga.sub.2 O.sub.3 material or thin layer comprises a minor component of metallic IrO.sub.2. The Ga.sub.2 O.sub.3 thin layer may be positioned using thermal evaporation (106) of Ga.sub.2 O.sub.3 or of a Ga.sub.2 O.sub.3 containing a compound from an Iridium crucible (108). Alternatively, the Ir may be co-evaporated (110) by electron beam evaporation. The electro-conductive ultraviolet light transmitting material Ga.sub.2 O.sub.3 with a metallic oxide phase is suitable for use on solar cells and in laser lithography.

Abstract: A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.

Abstract: A method of thermal processing a supporting structure comprised of various compound semiconductor layers having a Gd free Ga.sub.2 O.sub.3 surface layer including coating the surface layer with a dielectric or a metallic cap layer or combinations thereof, such that the low D.sub.it Ga.sub.2 O.sub.3 -compound semiconductor structure is conserved during thermal processing, e.g. during activation of ion implants of a self aligned metal-oxide-compound semiconductor gate structure. In a preferred embodiment, the semiconductor structure has a surface of GaAs, the Gd free Ga.sub.2 O.sub.3 layer has a thickness in a range of approximately 1 nm to 20 nm, and the insulating or metallic cap layer has a thickness in a range of approximately 1 nm to 500 nm.