Abstract: An in-cell touch screen and a display device are provided. In the in-cell touch screens, an insulation layer, in an area that each self-capacitance electrode overlap a wire, is provided with at least a first hole that runs through the insulation layer and each self-capacitance electrode is electrically connected with a corresponding wire via a corresponding first via hole; each self-capacitance electrode, within an area overlapping other wire than the corresponding wire and at a position corresponding to the first via hole, is disposed with a second via hole that runs through the self-capacitance electrode. An orthogonal projection of a second via hole on a lower substrate covers an orthogonal projection of a first via hole on the lower substrate. The in-cell touch screen can solve a problem of uneven image display due to nonuniform distribution of via holes in an insulation layer.

Abstract: An array substrate includes a base substrate, a thin film transistor and at least one photosensitive structure formed on the base substrate, the at least one photosensitive structure electrically connected to a drain electrode of the thin film transistor and configured to sense light intensity outside, and a common electrode formed on the base substrate on which the thin film transistor and the at least one photosensitive structure are formed. A method for manufacturing the array substrate, a control assembly and a display device are further disclosed.

Abstract: The present application discloses an array substrate comprising a first substrate, a first electrode on the first substrate, a passivation layer on a side of the first electrode distal to the first substrate, the passivation layer comprising a plurality of first vias, each of which corresponds to a different part of the first electrode, an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias, and a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias. The at least one electron emission source comprises a first portion having a first end and a second portion having a second end.

Abstract: A display screen, a pair of glasses, a display system and a playing method are provided. The display screen includes a display control module and a display panel. The display control module controls the display panel to display multiple frames of images according to multiple predetermined playing codes. Each playing code corresponds to one frame of image. Each frame of image is displayed as normal image or interference image based on different logic values of the corresponding playing code. The multiple frames of images are divided into multiple consecutive frame groups.

Abstract: Embodiments of the present application provide a method and a device for acquiring ECG data, and an ECG detection system. A method for acquiring ECG data, comprising: acquiring ECG signals of heart; performing a first-stage amplification on the ECG signals, a multiple of the first-stage amplification including 5 to 10 times; performing band-pass filtering process within a first frequency range on the ECG signals on which the first-stage amplification has been performed, the first frequency range being 0.1 Hz to 50 Hz; performing a second-stage amplification on the ECG signals on which the band-pass filtering process has been performed, a multiple of the second-stage amplification including 40 to 50 times; performing analog-to-digital conversion on the ECG signals on which the second-stage amplification has been performed, to generate ECG digital signals; and outputting the ECG digital signals.

Abstract: An array substrate includes a base substrate, a thin film transistor and at least one photosensitive structure formed on the base substrate, the at least one photosensitive structure electrically connected to a drain electrode of the thin film transistor and configured to sense light intensity outside, and a common electrode formed on the base substrate on which the thin film transistor and the at least one photosensitive structure are formed. A method for manufacturing the array substrate, a control assembly and a display device are further disclosed.

Abstract: The present disclosure describes a display Q_panel, a display panel and a manufacturing method thereof, as well as a display apparatus. The display Q_panel comprises a first and a second substrate for cell assembling to pre-form a plurality of display panels. The display Q_panel is provided, between the first substrate and the second substrate, with a blocking wall at the edge region on at least one side thereof, the blocking wall being located externally to the outmost cutting line on that side where it is located, and the sealant on that side being provided internally to the blocking wall. By providing a blocking wall externally to the outmost cutting line on the display Q_panel, the blocking wall blocks the spill-out of the sealant on that side, reduces the undesirable phenomena of sealant puncture, sealant break, etc. arising from the display panels after the cutting, can respond better to the Peel-off, Bending or other tests, and improves the robustness of glass cell assembling.

Abstract: The invention provides a display substrate and a manufacturing method thereof, and a display device. The display substrate comprises: a base, and gate lines and data lines, the data lines and the gate lines intersect with each other and are insulated from each other, the gate lines are electrically connected to a gate driver, the data lines are electrically connected to a source driver, the gate driver is provided at one side opposite to the source driver; gate signal lead-in lines, which are arranged parallel to the data lines; and an interlayer insulation layer provided between a layer in which the gate signal lead-in lines are arranged and a layer in which the gate lines are arranged, one end of each gate signal lead-in line is electrically connected to the gate driver, the other end thereof is connected to a gate line through a via penetrating the interlayer insulation layer.

Abstract: The present disclosure provides an in-cell touch panel and a display device, wherein each self-capacitance electrode is provided with a transversal slit within a region of the self-capacitance electrode corresponding to a gap between two adjacent pixel units in a column direction, and/or each self-capacitance electrode is provided with a longitudinal slit within a region of the self-capacitance electrode corresponding to a gap between two adjacent pixel units in a row direction, so that it can ensure that the slits in the self-capacitance electrodes and the gaps between the self-capacitance electrodes are uniformly arranged in the whole in-cell touch panel, thereby overcoming the defects such as bright lines, dark lines or the like in the in-cell touch panel.

Abstract: Embodiments of the present disclosure disclose an array substrate, a liquid crystal display panel and a display device. A strip shaped transparent and electrically conductive shielding electrode is arranged above a gate line, and an outer contour of a projection of the shielding electrode on a base substrate surrounds a projection of the gate line on the base substrate, and the shielding electrode is insulated from both a pixel electrode and the gate line. The shielding electrode can shield the electrical field above the gate line.

Abstract: A thin-film transistor (TFT) includes a gate electrode, a gate insulation layer, a source electrode, a drain electrode and an active layer arranged on a base substrate. The active layer includes an un-doped a-Si layer, a first doped a-Si layer and a second doped a-Si layer. One of the source electrode and the drain electrode is in contact with the first doped a-Si layer, and the other of the source electrode and the drain electrode is in contact with the second doped a-Si layer. The source electrode and the drain electrode are on different horizontal planes and spaced apart from each other, and the un-doped a-Si layer is positioned between the source electrode and the drain electrode.

Abstract: A display panel and a manufacturing method thereof and a display device are provided. The display panel includes an array substrate and an opposed substrate that are opposite to each other, and a liquid crystal layer located between the array substrate and the opposed substrate. The display panel includes a display area and a non-display area, a phase shift layer is disposed at the non-display area of the array substrate, and the phase shift layer is configured to shift a phase of light passing through the phase shift layer. The display panel is used to solve color cast problem when a TFT-LCD displays a pure color, which is caused by cross color when the display panel is viewed at a side angle.

Abstract: An in-cell touch panel and a display device are disclosed. The in-cell touch panel includes an array substrate provided with a plurality of sub-pixels, and a plurality of gate lines and a plurality of data lines that are disposed on the array substrate, intersected with each other and insulated from each other, a plurality of self capacitive electrodes which are disposed in a same layer and independent of each other, and a plurality of touch lines connecting the self capacitive electrodes to the touch detection chip; the plurality of gate lines and the plurality of data lines are intersected with each other to define the plurality of sub-pixels; each of the sub-pixels includes a pixel electrode and is configured with a long side and a short side; and the touch lines are disposed along the direction of short sides of the sub-pixels.

Abstract: The present application discloses an array substrate comprising a first substrate, a first electrode on the first substrate, a passivation layer on a side of the first electrode distal to the first substrate, the passivation layer comprising a plurality of first vias, each of which corresponds to a different part of the first electrode, an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias, and a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias. The at least one electron emission source comprises a first portion having a first end and a second portion having a second end.

Abstract: The present disclosure provides a shift register circuit, which includes a first switch unit connecting an input end to a first node when a positive-phase clock signal is at a first level; a second switch unit applying a negative-phase clock signal to an output end when the first node is at the first level; a positive feedback unit enabling the second node to be at a second level when the first node is at the first level and enabling the first node to be at the second level when the second node is at the first level; a third switch unit enabling a third node to be at the first level when the positive-phase clock signal is at the first level; a fourth switch unit connecting the second node to the third node when the negative-phase clock signal is at the first level; and a fifth switch unit.

Abstract: The present application discloses an array substrate comprising a first substrate, a first electrode on the first substrate, a passivation layer on a side of the first electrode distal to the first substrate, the passivation layer comprising a plurality of first vias, each of which corresponds to a different part of the first electrode, an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias, and a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias. The at least one electron emission source comprises a first portion having a first end and a second portion having a second end.

Abstract: A sealant, a preparation method and a curing method thereof, and a display apparatus are provided. The sealant includes a viscous transparent base material and electrochromic material doped in the base material. The electrochromic material is mutually linked to form a conductive chain and can change color in the case that an electric field is applied upon the electrochromic material, to prevent light from passing through.

Abstract: A shift register unit includes a pull-down maintenance module configured to pull down potentials at a pull-up node and a gate signal output end; a reset module configured to, at a touch stage within one frame of time, reset a potential of a signal from the gate signal output end to a potential of a fourth signal; a first signal output control module configured to, at a display stage within one frame of time, control a first signal output end to output a first common electrode signal, and at the touch stage within one frame of time, control the first signal output end to output a first signal input in the first signal input end. The first signal is a signal inputted at the touch stage to a common electrode connected to the shift register unit.

Abstract: The present disclosure provides a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor comprises a gate layer, a source and a drain located on the gate layer, and an active layer located on the source and the drain. The active layer is electrically connected to the source and the drain. The active layer comprises two sides arranged in parallel, and each side forms an acute angle of 45° with a face of the drain facing the source.

Abstract: The present disclosure provides a shift register circuit, which includes a first switch unit connecting an input end to a first node when a positive-phase clock signal is at a first level; a second switch unit applying a negative-phase clock signal to an output end when the first node is at the first level; a positive feedback unit enabling the second node to be at a second level when the first node is at the first level and enabling the first node to be at the second level when the second node is at the first level; a third switch unit enabling a third node to be at the first level when the positive-phase clock signal is at the first level; a fourth switch unit connecting the second node to the third node when the negative-phase clock signal is at the first level; and a fifth switch unit.