Patents by Inventor Zhi Yong Han

Zhi Yong Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor local interconnect and contact
    Patent number: 8304834
    Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: November 6, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
  • SEMICONDUCTOR LOCAL INTERCONNECT AND CONTACT
    Publication number: 20060281253
    Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
    Type: Application
    Filed: August 22, 2006
    Publication date: December 14, 2006
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Pradeep Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
  • Semiconductor local interconnect and contact
    Patent number: 7119005
    Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: October 10, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
  • Method of manufacturing semiconductor local interconnect and contact
    Patent number: 6884712
    Abstract: An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: April 26, 2005
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Pradeep Yelehanka, Tong Qing Chen, Zhi Yong Han, Zhen Jia Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
  • Method of manufacturing semiconductor local interconnect and contact
    Publication number: 20040155269
    Abstract: An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
    Type: Application
    Filed: February 7, 2003
    Publication date: August 12, 2004
    Applicant: Chartered Semiconductor Mfg. Ltd.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah